2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
108 lines
3.3 KiB
C
108 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* IRQ mappings for Loongson 1
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*/
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#ifndef __ASM_MACH_LOONGSON32_IRQ_H
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#define __ASM_MACH_LOONGSON32_IRQ_H
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/*
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* CPU core Interrupt Numbers
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*/
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#define MIPS_CPU_IRQ_BASE 0
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#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
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#define SOFTINT0_IRQ MIPS_CPU_IRQ(0)
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#define SOFTINT1_IRQ MIPS_CPU_IRQ(1)
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#define INT0_IRQ MIPS_CPU_IRQ(2)
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#define INT1_IRQ MIPS_CPU_IRQ(3)
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#define INT2_IRQ MIPS_CPU_IRQ(4)
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#define INT3_IRQ MIPS_CPU_IRQ(5)
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#define INT4_IRQ MIPS_CPU_IRQ(6)
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#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */
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#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
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/*
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* INT0~3 Interrupt Numbers
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*/
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#define LS1X_IRQ_BASE MIPS_CPU_IRQS
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#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
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#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
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#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
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#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define LS1X_UART1_IRQ LS1X_IRQ(0, 4)
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#define LS1X_UART2_IRQ LS1X_IRQ(0, 5)
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#endif
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#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
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#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
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#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
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#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9)
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#define LS1X_AC97_IRQ LS1X_IRQ(0, 10)
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#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
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#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
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#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
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#if defined(CONFIG_LOONGSON1_LS1C)
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#define LS1X_NAND_IRQ LS1X_IRQ(0, 16)
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#endif
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#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
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#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
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#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
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#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20)
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#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
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#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
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#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
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#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
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#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
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#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
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#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
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#define LS1X_UART4_IRQ LS1X_IRQ(0, 29)
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#define LS1X_UART5_IRQ LS1X_IRQ(0, 30)
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define LS1X_UART3_IRQ LS1X_IRQ(0, 29)
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#define LS1X_ADC_IRQ LS1X_IRQ(0, 30)
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#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31)
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#endif
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#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
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#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
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#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define LS1X_OTG_IRQ LS1X_IRQ(1, 2)
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#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3)
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#define LS1X_CAM_IRQ LS1X_IRQ(1, 4)
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#define LS1X_UART4_IRQ LS1X_IRQ(1, 5)
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#define LS1X_UART5_IRQ LS1X_IRQ(1, 6)
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#define LS1X_UART6_IRQ LS1X_IRQ(1, 7)
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#define LS1X_UART7_IRQ LS1X_IRQ(1, 8)
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#define LS1X_UART8_IRQ LS1X_IRQ(1, 9)
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#define LS1X_UART9_IRQ LS1X_IRQ(1, 13)
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#define LS1X_UART10_IRQ LS1X_IRQ(1, 14)
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#define LS1X_UART11_IRQ LS1X_IRQ(1, 15)
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#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17)
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#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18)
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#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19)
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#endif
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define INTN 4
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define INTN 5
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#endif
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#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)
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#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
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#endif /* __ASM_MACH_LOONGSON32_IRQ_H */
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