Daniel Jurgens b47bd6ea40 {net, ib}/mlx5: Make cache line size determination at runtime.
ARM 64B cache line systems have L1_CACHE_BYTES set to 128.
cache_line_size() will return the correct size.

Fixes: cf50b5efa2fe('net/mlx5_core/ib: New device capabilities
handling.')
Signed-off-by: Daniel Jurgens <danielj@mellanox.com>

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-29 12:00:39 -04:00
..
2016-09-22 13:22:21 +02:00
2016-10-05 16:43:53 -03:00
2016-09-30 18:40:40 +02:00
2016-10-12 11:01:37 -07:00
2016-10-06 11:19:10 -07:00