linux

iv/linux

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Sergey Matyukevich b49f700668

riscv: mm: fix regression due to update_mmu_cache change

This is a partial revert of the commit 4bd1d80efb5a ("riscv: mm: notify
remote harts about mmu cache updates"). Original commit included two
loosely related changes serving the same purpose of fixing stale TLB
entries causing user-space application crash:
- introduce deferred per-ASID TLB flush for CPUs not running the task
- switch to per-ASID TLB flush on all CPUs running the task in update_mmu_cache

According to report and discussion in [1], the second part caused a
regression on Renesas RZ/Five SoC. For now restore the old behavior
of the update_mmu_cache.

[1] https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/

Fixes: 4bd1d80efb5a ("riscv: mm: notify remote harts about mmu cache updates")
Reported-by: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Link: trailer, so that it can be parsed with git's trailer functionality?
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230129211818.686557-1-geomatsi@gmail.com
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

2023-02-21 17:21:09 -08:00

boot

RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO

2022-12-27 18:01:40 +00:00

configs

RISC-V Patches for the 6.2 Merge Window, Part 1

2022-12-14 15:23:49 -08:00

errata

riscv: Fix early alternative patching

2023-02-14 16:10:35 -08:00

include

riscv: mm: fix regression due to update_mmu_cache change