0c6ab1b8f8
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Move to devm provider registration, NUL terminate frequency table, made tristate/modular] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
23 lines
482 B
Plaintext
23 lines
482 B
Plaintext
Qualcomm MSM8916 A53 PLL Binding
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The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies
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above 1GHz.
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Required properties :
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- compatible : Shall contain only one of the following:
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"qcom,msm8916-a53pll"
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- reg : shall contain base register location and length
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- #clock-cells : must be set to <0>
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Example:
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a53pll: clock@b016000 {
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compatible = "qcom,msm8916-a53pll";
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reg = <0xb016000 0x40>;
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#clock-cells = <0>;
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};
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