daeeb438c0
HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
29 lines
762 B
Plaintext
29 lines
762 B
Plaintext
Binding for the HSDK Generic PLL clock
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible: should be "snps,hsdk-<name>-pll-clock"
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"snps,hsdk-core-pll-clock"
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"snps,hsdk-gp-pll-clock"
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"snps,hsdk-hdmi-pll-clock"
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- reg : should contain base register location and length.
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- clocks: shall be the input parent clock phandle for the PLL.
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- #clock-cells: from common clock binding; Should always be set to 0.
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Example:
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input_clk: input-clk {
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clock-frequency = <33333333>;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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cpu_clk: cpu-clk@0 {
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compatible = "snps,hsdk-core-pll-clock";
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reg = <0x00 0x10>;
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#clock-cells = <0>;
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clocks = <&input_clk>;
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};
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