d440c4d360
Qualcom IPQ8074 SoC uses QPIC NAND controller version 1.5.0 which uses BAM DMA Engine. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
140 lines
3.5 KiB
Plaintext
140 lines
3.5 KiB
Plaintext
* Qualcomm NAND controller
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Required properties:
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- compatible: must be one of the following:
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* "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
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SoC and it uses ADM DMA
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* "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
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IPQ4019 SoC and it uses BAM DMA
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* "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
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IPQ8074 SoC and it uses BAM DMA
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- reg: MMIO address range
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- clocks: must contain core clock and always on clock
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- clock-names: must contain "core" for the core clock and "aon" for the
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always on clock
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EBI2 specific properties:
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- dmas: DMA specifier, consisting of a phandle to the ADM DMA
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controller node and the channel number to be used for
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NAND. Refer to dma.txt and qcom_adm.txt for more details
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- dma-names: must be "rxtx"
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- qcom,cmd-crci: must contain the ADM command type CRCI block instance
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number specified for the NAND controller on the given
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platform
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- qcom,data-crci: must contain the ADM data type CRCI block instance
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number specified for the NAND controller on the given
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platform
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QPIC specific properties:
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- dmas: DMA specifier, consisting of a phandle to the BAM DMA
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and the channel number to be used for NAND. Refer to
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dma.txt, qcom_bam_dma.txt for more details
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- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
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- #address-cells: <1> - subnodes give the chip-select number
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- #size-cells: <0>
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* NAND chip-select
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Each controller may contain one or more subnodes to represent enabled
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chip-selects which (may) contain NAND flash chips. Their properties are as
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follows.
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Required properties:
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- reg: a single integer representing the chip-select
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number (e.g., 0, 1, 2, etc.)
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- #address-cells: see partition.txt
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- #size-cells: see partition.txt
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- nand-ecc-strength: see nand.txt
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- nand-ecc-step-size: must be 512. see nand.txt for more details.
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Optional properties:
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- nand-bus-width: see nand.txt
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Each nandcs device node may optionally contain a 'partitions' sub-node, which
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further contains sub-nodes describing the flash partition mapping. See
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partition.txt for more detail.
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Example:
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nand-controller@1ac00000 {
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compatible = "qcom,ipq806x-nand";
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reg = <0x1ac00000 0x800>;
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clocks = <&gcc EBI2_CLK>,
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<&gcc EBI2_AON_CLK>;
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clock-names = "core", "aon";
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dmas = <&adm_dma 3>;
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dma-names = "rxtx";
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qcom,cmd-crci = <15>;
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qcom,data-crci = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "boot-nand";
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reg = <0 0x58a0000>;
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};
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partition@58a0000 {
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label = "fs-nand";
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reg = <0x58a0000 0x4000000>;
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};
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};
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};
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};
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nand-controller@79b0000 {
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compatible = "qcom,ipq4019-nand";
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reg = <0x79b0000 0x1000>;
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clocks = <&gcc GCC_QPIC_CLK>,
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<&gcc GCC_QPIC_AHB_CLK>;
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clock-names = "core", "aon";
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dmas = <&qpicbam 0>,
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<&qpicbam 1>,
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<&qpicbam 2>;
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dma-names = "tx", "rx", "cmd";
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "boot-nand";
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reg = <0 0x58a0000>;
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};
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partition@58a0000 {
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label = "fs-nand";
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reg = <0x58a0000 0x4000000>;
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};
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};
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};
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};
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