a185048ca8
new per SoC interface instead legacy interface with lots of un-used field that only cause confusion model pp_smu like one of our HW objects with func_ptr interface to call into it. struct pp_smu as handle to call pp/smu Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
132 lines
3.5 KiB
C
132 lines
3.5 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DM_PP_SMU_IF__H
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#define DM_PP_SMU_IF__H
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/*
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* interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
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*/
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struct pp_smu {
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struct dc_context *ctx;
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};
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enum wm_set_id {
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WM_A,
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WM_B,
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WM_C,
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WM_D,
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WM_COUNT,
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};
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struct pp_smu_wm_set_range {
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enum wm_set_id wm_inst;
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uint32_t min_fill_clk_khz;
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uint32_t max_fill_clk_khz;
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uint32_t min_drain_clk_khz;
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uint32_t max_drain_clk_khz;
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};
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struct pp_smu_wm_range_sets {
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uint32_t num_reader_wm_sets;
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struct pp_smu_wm_set_range reader_wm_sets[WM_COUNT];
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uint32_t num_writer_wm_sets;
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struct pp_smu_wm_set_range writer_wm_sets[WM_COUNT];
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};
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struct pp_smu_display_requirement_rv {
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/* PPSMC_MSG_SetDisplayCount: count
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* 0 triggers S0i2 optimization
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*/
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unsigned int display_count;
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/* PPSMC_MSG_SetHardMinFclkByFreq: khz
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* FCLK will vary with DPM, but never below requested hard min
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*/
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unsigned int hard_min_fclk_khz;
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/* PPSMC_MSG_SetHardMinDcefclkByFreq: khz
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* fixed clock at requested freq, either from FCH bypass or DFS
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*/
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unsigned int hard_min_dcefclk_khz;
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/* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz
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* when DF is in cstate, dcf clock is further divided down
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* to just above given frequency
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*/
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unsigned int min_deep_sleep_dcefclk_mhz;
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};
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struct pp_smu_funcs_rv {
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struct pp_smu pp_smu;
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void (*set_display_requirement)(struct pp_smu *pp,
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struct pp_smu_display_requirement_rv *req);
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/* which SMU message? are reader and writer WM separate SMU msg? */
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void (*set_wm_ranges)(struct pp_smu *pp,
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struct pp_smu_wm_range_sets *ranges);
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};
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#if 0
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struct pp_smu_funcs_rv {
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/* PPSMC_MSG_SetDisplayCount
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* 0 triggers S0i2 optimization
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*/
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void (*set_display_count)(struct pp_smu *pp, int count);
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/* PPSMC_MSG_SetHardMinFclkByFreq
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* FCLK will vary with DPM, but never below requested hard min
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*/
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void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz);
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/* PPSMC_MSG_SetHardMinDcefclkByFreq
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* fixed clock at requested freq, either from FCH bypass or DFS
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*/
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void (*set_hard_min_dcefclk_by_freq)(struct pp_smu *pp, int khz);
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/* PPSMC_MSG_SetMinDeepSleepDcefclk
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* when DF is in cstate, dcf clock is further divided down
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* to just above given frequency
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*/
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void (*set_min_deep_sleep_dcefclk)(struct pp_smu *pp, int mhz);
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/* todo: aesthetic
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* watermark range table
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*/
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/* todo: functional/feature
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* PPSMC_MSG_SetHardMinSocclkByFreq: required to support DWB
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*/
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};
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#endif
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#endif /* DM_PP_SMU_IF__H */
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