10cf8300ec
Our chosen byte swapping, which is what firmware already uses, is to do readl/writel by normal lw/sw intructions (data invariance). This also means we need to mangle addresses for u8 and u16 accesses. The mangling for 16bit has been done aready, but 8bit one was missing. Correcting this causes different addresses for accesses to the SuperIO and local bus of the IOC3 chip. This is fixed by changing byte order in ioc3 and m48rtc_rtc structs. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: David S. Miller <davem@davemloft.net> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: netdev@vger.kernel.org Cc: linux-rtc@vger.kernel.org
26 lines
787 B
C
26 lines
787 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Ralf Baechle
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*/
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#ifndef __ASM_MACH_IP27_MANGLE_PORT_H
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#define __ASM_MACH_IP27_MANGLE_PORT_H
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#define __swizzle_addr_b(port) ((port) ^ 3)
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#define __swizzle_addr_w(port) ((port) ^ 2)
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#define __swizzle_addr_l(port) (port)
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#define __swizzle_addr_q(port) (port)
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# define ioswabb(a, x) (x)
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# define __mem_ioswabb(a, x) (x)
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# define ioswabw(a, x) (x)
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# define __mem_ioswabw(a, x) cpu_to_le16(x)
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# define ioswabl(a, x) (x)
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# define __mem_ioswabl(a, x) cpu_to_le32(x)
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# define ioswabq(a, x) (x)
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# define __mem_ioswabq(a, x) cpu_to_le64(x)
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#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
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