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Dmitry Rokosov b6ec400aa1 clk: meson: introduce new pll power-on sequence for A1 SoC family 
Modern meson PLL IPs are a little bit different from early known PLLs.
The main difference is located in the init/enable/disable sequences; the
rate logic is the same.

In A1 PLL, the PLL enable sequence is different, so add new optional pll
reg bits and use the new power-on sequence to enable the PLL:
    1. enable the pll, delay for 10us
    2. enable the pll self-adaption current module, delay for 40us
    3. enable the lock detect module

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230523135351.19133-3-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-30 17:53:00 +02:00
..
axg-aoclk.c
clk: meson: enable building as modules
2020-11-23 09:08:23 +01:00
axg-aoclk.h
clk: meson: axg-ao: add 32k generation subtree
2019-01-07 15:21:43 +01:00
axg-audio.c
clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()
2022-06-15 19:22:29 -07:00
axg-audio.h
clk: meson: axg_audio: add sm1 support
2019-10-08 09:29:23 +02:00
axg.c
clk: meson: axg: Remove MIPI enable clock gate
2021-02-09 13:32:59 +01:00
axg.h
clk: meson: axg: Remove MIPI enable clock gate
2021-02-09 13:32:59 +01:00
clk-cpu-dyndiv.c
clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
2023-01-13 15:14:12 +01:00
clk-cpu-dyndiv.h
clk: meson: add g12a cpu dynamic divider driver
2019-08-09 12:10:03 +02:00
clk-dualdiv.c
clk: meson: dualdiv: switch from .round_rate to .determine_rate
2023-01-13 15:14:12 +01:00
clk-dualdiv.h
clk: meson: rework and clean drivers dependencies
2019-02-02 17:43:32 +01:00
clk-mpll.c
clk: meson: mpll: Switch from .round_rate to .determine_rate
2023-01-13 15:14:12 +01:00
clk-mpll.h
clk: meson: mpll: add init callback and regs
2019-05-20 12:19:29 +02:00
clk-phase.c
clk: meson: add sclk-ws driver
2020-08-17 15:58:02 +02:00
clk-phase.h
clk: meson: add sclk-ws driver
2020-08-17 15:58:02 +02:00
clk-pll.c
clk: meson: introduce new pll power-on sequence for A1 SoC family
2023-05-30 17:53:00 +02:00
clk-pll.h
clk: meson: introduce new pll power-on sequence for A1 SoC family
2023-05-30 17:53:00 +02:00
clk-regmap.c
clk: meson: regmap: switch to determine_rate for the dividers
2021-06-30 11:37:02 -07:00
clk-regmap.h
clk: define to_clk_regmap() as inline function
2020-10-28 16:34:44 -07:00
g12a-aoclk.c
clk: meson: enable building as modules
2020-11-23 09:08:23 +01:00
g12a-aoclk.h
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
2019-04-01 10:45:11 +02:00
g12a.c
clk: meson: g12a: Add missing NNA source clocks for g12b
2021-06-09 21:39:50 +02:00
g12a.h
clk: meson: g12a: add MIPI DSI Host Pixel Clock
2020-11-26 15:25:20 +01:00
gxbb-aoclk.c
clk: meson: enable building as modules
2020-11-23 09:08:23 +01:00
gxbb-aoclk.h
clk: meson: gxbb-ao: replace cec-32k with the dual divider
2019-01-07 15:21:22 +01:00
gxbb.c
clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB
2021-11-30 10:28:52 +01:00
gxbb.h
clk: meson: gxbb: add the gxl internal dac gate
2020-02-13 17:26:04 +01:00
Kconfig
clk: meson: enable building as modules
2020-11-23 09:08:23 +01:00
Makefile
clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
2019-12-11 14:06:29 +01:00
meson8-ddr.c
clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
2019-12-11 14:06:29 +01:00
meson8b.c
clk: meson: Hold reference returned by of_get_parent()
2022-08-19 14:29:00 -07:00
meson8b.h
clk: meson: meson8b: Initialize the HDMI PLL registers
2021-09-23 11:46:37 +02:00
meson-aoclk.c
clk: meson: Hold reference returned by of_get_parent()
2022-08-19 14:29:00 -07:00
meson-aoclk.h
clk: meson: remove ao input bypass clocks
2019-07-29 12:42:48 +02:00
meson-eeclk.c
clk: meson: Hold reference returned by of_get_parent()
2022-08-19 14:29:00 -07:00
meson-eeclk.h
clk: meson: remove ee input bypass clocks
2019-07-29 12:42:49 +02:00
parm.h
clk: meson: rework and clean drivers dependencies
2019-02-02 17:43:32 +01:00
sclk-div.c
clk: meson: sclk-div: switch from .round_rate to .determine_rate
2023-01-13 15:14:12 +01:00
sclk-div.h
clk: meson: rework and clean drivers dependencies
2019-02-02 17:43:32 +01:00
vid-pll-div.c
clk: meson: vid-pll-div: remove warning and return 0 on invalid config
2019-03-29 09:41:30 +01:00
vid-pll-div.h
clk: meson: rework and clean drivers dependencies
2019-02-02 17:43:32 +01:00