Sumit Gupta b713442214 soc/tegra: cbb: Add CBB 1.0 driver for Tegra194 ... Adding driver to handle errors from Control Backbone (CBB) which are generated due to illegal accesses. CBB 1.0 is used in Tegra194 SoCs. When an error is reported from a NOC within CBB, the driver prints debug information about failed transaction like Error Code, Error Description, Master, Address, AXI ID, Cache, Protection, Security Group etc. It then causes system crash using BUG_ON() or call WARN() based on whether the error type is fatal or not. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2022-09-15 12:41:36 +02:00
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arc	clocksource/drivers/arc_timer: Eliminate redefined macro error	2021-10-16 22:15:01 +02:00
at91	ARM: at91: PM: add cpu idle support for sama7g5	2022-02-25 12:36:25 +01:00
bcm2835	firmware: raspberrypi: Add RPI_FIRMWARE_NOTIFY_DISPLAY_DONE	2022-01-11 13:16:10 +01:00
canaan	clk: Add RISC-V Canaan Kendryte K210 clock driver	2021-02-22 17:51:04 -08:00
fsl	crypto: caam - add in-kernel interface for blob generator	2022-05-23 18:47:50 +03:00
imx	ARM: imx: Initialize SoC ID on i.MX50	2021-05-13 15:42:21 +08:00
mediatek	media: memory: mtk-smi: Get rid of mtk_smi_larb_get/put	2022-01-28 15:30:21 +01:00
microchip	soc: add microchip polarfire soc system controller	2022-02-25 12:50:59 +01:00
mscc	net: dsa: felix: keep reference on entire tc-taprio config	2022-06-30 21:18:15 -07:00
qcom	mfd: qcom-spmi-pmic: read fab id on supported PMICs	2022-06-18 14:01:16 +01:00
rockchip	soc: rockchip: power-domain: Manage resource conflicts with firmware	2022-05-09 03:36:52 +09:00
sa1100	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
sifive	riscv: move sifive_l2_cache.h to include/soc	2020-01-12 10:12:44 -08:00
tegra	soc/tegra: cbb: Add CBB 1.0 driver for Tegra194	2022-09-15 12:41:36 +02:00