Dinh Nguyen b89cd950cb clk: socfpga: Support multiple parents for the pll clocks ...

The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

2014-02-26 12:23:40 -08:00

..

clk-gate.c

clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"

2014-02-18 14:08:14 -08:00

clk-periph.c

clk: socfpga: split clk code

2014-02-18 14:08:13 -08:00

clk-pll.c

clk: socfpga: Support multiple parents for the pll clocks

2014-02-26 12:23:40 -08:00

clk.c

clk: socfpga: split clk code

2014-02-18 14:08:13 -08:00

clk.h

clk: socfpga: split clk code

2014-02-18 14:08:13 -08:00

Makefile

clk: socfpga: split clk code

2014-02-18 14:08:13 -08:00