1802d0beec
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
139 lines
2.1 KiB
ArmAsm
139 lines
2.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 Broadcom Corporation
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*/
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/bmips.h>
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#include "pm.h"
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.text
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.set noreorder
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.align 5
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.global s3_reentry
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/*
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* a0: AON_CTRL base register
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* a1: D-Cache line size
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*/
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LEAF(brcm_pm_do_s3)
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/* Get the address of s3_context */
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la t0, gp_regs
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sw ra, 0(t0)
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sw s0, 4(t0)
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sw s1, 8(t0)
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sw s2, 12(t0)
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sw s3, 16(t0)
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sw s4, 20(t0)
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sw s5, 24(t0)
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sw s6, 28(t0)
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sw s7, 32(t0)
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sw gp, 36(t0)
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sw sp, 40(t0)
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sw fp, 44(t0)
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/* Save CP0 Status */
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mfc0 t1, CP0_STATUS
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sw t1, 48(t0)
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/* Write-back gp registers - cache will be gone */
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addiu t1, a1, -1
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not t1
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and t0, t1
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/* Flush at least 64 bytes */
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addiu t2, t0, 64
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and t2, t1
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1: cache 0x17, 0(t0)
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bne t0, t2, 1b
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addu t0, a1
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/* Drop to deep standby */
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li t1, PM_WARM_CONFIG
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sw zero, AON_CTRL_PM_CTRL(a0)
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lw zero, AON_CTRL_PM_CTRL(a0)
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sw t1, AON_CTRL_PM_CTRL(a0)
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lw t1, AON_CTRL_PM_CTRL(a0)
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li t1, (PM_WARM_CONFIG | PM_PWR_DOWN)
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sw t1, AON_CTRL_PM_CTRL(a0)
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lw t1, AON_CTRL_PM_CTRL(a0)
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/* Enable CP0 interrupt 2 and wait for interrupt */
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mfc0 t0, CP0_STATUS
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li t1, ~(ST0_IM | ST0_IE)
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and t0, t1
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ori t0, STATUSF_IP2
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mtc0 t0, CP0_STATUS
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nop
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nop
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nop
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ori t0, ST0_IE
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mtc0 t0, CP0_STATUS
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/* Wait for interrupt */
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wait
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nop
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s3_reentry:
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/* Clear call/return stack */
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li t0, (0x06 << 16)
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mtc0 t0, $22, 2
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ssnop
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ssnop
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ssnop
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/* Clear jump target buffer */
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li t0, (0x04 << 16)
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mtc0 t0, $22, 2
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ssnop
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ssnop
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ssnop
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sync
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nop
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/* Setup mmu defaults */
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mtc0 zero, CP0_WIRED
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mtc0 zero, CP0_ENTRYHI
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li k0, PM_DEFAULT_MASK
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mtc0 k0, CP0_PAGEMASK
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li sp, BMIPS_WARM_RESTART_VEC
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la k0, plat_wired_tlb_setup
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jalr k0
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nop
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/* Restore general purpose registers */
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la t0, gp_regs
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lw fp, 44(t0)
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lw sp, 40(t0)
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lw gp, 36(t0)
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lw s7, 32(t0)
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lw s6, 28(t0)
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lw s5, 24(t0)
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lw s4, 20(t0)
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lw s3, 16(t0)
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lw s2, 12(t0)
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lw s1, 8(t0)
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lw s0, 4(t0)
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lw ra, 0(t0)
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/* Restore CP0 status */
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lw t1, 48(t0)
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mtc0 t1, CP0_STATUS
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/* Return to caller */
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li v0, 0
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jr ra
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nop
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END(brcm_pm_do_s3)
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