b992131aac
Dp_intf supports YUV422 as output format. In MT8195 Chrome project, YUV422 output format is used for 4K resolution. To support this, it is also needed to support color format transfer. Color format transfer is a new feature for both dpi and dpintf of MT8195. The input format could be RGB888 and output format for dp_intf should be YUV422. Therefore, we add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format. Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220705102530.1344-2-rex-bc.chen@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
1032 lines
26 KiB
C
1032 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_graph.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <video/videomode.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_bridge_connector.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_of.h>
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#include <drm/drm_simple_kms_helper.h>
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#include "mtk_disp_drv.h"
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#include "mtk_dpi_regs.h"
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#include "mtk_drm_ddp_comp.h"
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enum mtk_dpi_out_bit_num {
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MTK_DPI_OUT_BIT_NUM_8BITS,
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MTK_DPI_OUT_BIT_NUM_10BITS,
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MTK_DPI_OUT_BIT_NUM_12BITS,
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MTK_DPI_OUT_BIT_NUM_16BITS
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};
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enum mtk_dpi_out_yc_map {
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MTK_DPI_OUT_YC_MAP_RGB,
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MTK_DPI_OUT_YC_MAP_CYCY,
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MTK_DPI_OUT_YC_MAP_YCYC,
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MTK_DPI_OUT_YC_MAP_CY,
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MTK_DPI_OUT_YC_MAP_YC
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};
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enum mtk_dpi_out_channel_swap {
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MTK_DPI_OUT_CHANNEL_SWAP_RGB,
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MTK_DPI_OUT_CHANNEL_SWAP_GBR,
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MTK_DPI_OUT_CHANNEL_SWAP_BRG,
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MTK_DPI_OUT_CHANNEL_SWAP_RBG,
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MTK_DPI_OUT_CHANNEL_SWAP_GRB,
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MTK_DPI_OUT_CHANNEL_SWAP_BGR
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};
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enum mtk_dpi_out_color_format {
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MTK_DPI_COLOR_FORMAT_RGB,
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MTK_DPI_COLOR_FORMAT_YCBCR_422
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};
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struct mtk_dpi {
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struct drm_encoder encoder;
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct drm_connector *connector;
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void __iomem *regs;
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struct device *dev;
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struct clk *engine_clk;
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struct clk *pixel_clk;
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struct clk *tvd_clk;
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int irq;
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struct drm_display_mode mode;
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const struct mtk_dpi_conf *conf;
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enum mtk_dpi_out_color_format color_format;
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enum mtk_dpi_out_yc_map yc_map;
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enum mtk_dpi_out_bit_num bit_num;
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enum mtk_dpi_out_channel_swap channel_swap;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_gpio;
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struct pinctrl_state *pins_dpi;
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u32 output_fmt;
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int refcount;
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};
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static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
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{
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return container_of(b, struct mtk_dpi, bridge);
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}
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enum mtk_dpi_polarity {
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MTK_DPI_POLARITY_RISING,
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MTK_DPI_POLARITY_FALLING,
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};
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struct mtk_dpi_polarities {
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enum mtk_dpi_polarity de_pol;
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enum mtk_dpi_polarity ck_pol;
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enum mtk_dpi_polarity hsync_pol;
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enum mtk_dpi_polarity vsync_pol;
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};
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struct mtk_dpi_sync_param {
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u32 sync_width;
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u32 front_porch;
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u32 back_porch;
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bool shift_half_line;
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};
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struct mtk_dpi_yc_limit {
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u16 y_top;
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u16 y_bottom;
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u16 c_top;
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u16 c_bottom;
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};
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/**
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* struct mtk_dpi_conf - Configuration of mediatek dpi.
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* @cal_factor: Callback function to calculate factor value.
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* @reg_h_fre_con: Register address of frequency control.
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* @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
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* @edge_sel_en: Enable of edge selection.
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* @output_fmts: Array of supported output formats.
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* @num_output_fmts: Quantity of supported output formats.
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* @is_ck_de_pol: Support CK/DE polarity.
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* @swap_input_support: Support input swap function.
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* @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
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* (no shift).
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* @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
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* @channel_swap_shift: Shift value of channel swap.
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* @yuv422_en_bit: Enable bit of yuv422.
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* @csc_enable_bit: Enable bit of CSC.
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*/
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struct mtk_dpi_conf {
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unsigned int (*cal_factor)(int clock);
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u32 reg_h_fre_con;
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u32 max_clock_khz;
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bool edge_sel_en;
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const u32 *output_fmts;
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u32 num_output_fmts;
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bool is_ck_de_pol;
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bool swap_input_support;
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u32 dimension_mask;
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u32 hvsize_mask;
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u32 channel_swap_shift;
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u32 yuv422_en_bit;
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u32 csc_enable_bit;
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};
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static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
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{
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u32 tmp = readl(dpi->regs + offset) & ~mask;
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tmp |= (val & mask);
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writel(tmp, dpi->regs + offset);
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}
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static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
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{
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mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
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}
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static void mtk_dpi_enable(struct mtk_dpi *dpi)
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{
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mtk_dpi_mask(dpi, DPI_EN, EN, EN);
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}
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static void mtk_dpi_disable(struct mtk_dpi *dpi)
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{
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mtk_dpi_mask(dpi, DPI_EN, 0, EN);
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}
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static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW,
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dpi->conf->dimension_mask << HPW);
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mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP,
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dpi->conf->dimension_mask << HBP);
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mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
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dpi->conf->dimension_mask << HFP);
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}
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static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync,
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u32 width_addr, u32 porch_addr)
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{
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mtk_dpi_mask(dpi, width_addr,
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sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
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VSYNC_HALF_LINE_MASK);
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mtk_dpi_mask(dpi, width_addr,
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sync->sync_width << VSYNC_WIDTH_SHIFT,
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dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT);
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mtk_dpi_mask(dpi, porch_addr,
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sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
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dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT);
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mtk_dpi_mask(dpi, porch_addr,
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sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
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dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT);
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}
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static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
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}
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static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN,
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DPI_TGEN_VPORCH_LEVEN);
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}
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static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD,
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DPI_TGEN_VPORCH_RODD);
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}
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static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN,
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DPI_TGEN_VPORCH_REVEN);
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}
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static void mtk_dpi_config_pol(struct mtk_dpi *dpi,
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struct mtk_dpi_polarities *dpi_pol)
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{
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unsigned int pol;
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unsigned int mask;
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mask = HSYNC_POL | VSYNC_POL;
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pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
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(dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
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if (dpi->conf->is_ck_de_pol) {
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mask |= CK_POL | DE_POL;
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pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ?
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0 : CK_POL) |
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(dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ?
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0 : DE_POL);
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}
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mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask);
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}
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static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
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{
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mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN);
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}
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static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
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{
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mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN);
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}
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static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
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{
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mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE,
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dpi->conf->hvsize_mask << HSIZE);
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mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE,
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dpi->conf->hvsize_mask << VSIZE);
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}
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static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi)
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{
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struct mtk_dpi_yc_limit limit;
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if (drm_default_rgb_quant_range(&dpi->mode) ==
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HDMI_QUANTIZATION_RANGE_LIMITED) {
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limit.y_bottom = 0x10;
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limit.y_top = 0xfe0;
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limit.c_bottom = 0x10;
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limit.c_top = 0xfe0;
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} else {
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limit.y_bottom = 0;
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limit.y_top = 0xfff;
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limit.c_bottom = 0;
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limit.c_top = 0xfff;
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}
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mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT,
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Y_LIMINT_BOT_MASK);
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mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP,
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Y_LIMINT_TOP_MASK);
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mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT,
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C_LIMIT_BOT_MASK);
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mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP,
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C_LIMIT_TOP_MASK);
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}
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static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi,
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enum mtk_dpi_out_bit_num num)
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{
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u32 val;
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switch (num) {
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case MTK_DPI_OUT_BIT_NUM_8BITS:
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val = OUT_BIT_8;
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break;
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case MTK_DPI_OUT_BIT_NUM_10BITS:
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val = OUT_BIT_10;
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break;
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case MTK_DPI_OUT_BIT_NUM_12BITS:
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val = OUT_BIT_12;
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break;
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case MTK_DPI_OUT_BIT_NUM_16BITS:
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val = OUT_BIT_16;
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break;
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default:
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val = OUT_BIT_8;
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break;
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}
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mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT,
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OUT_BIT_MASK);
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}
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static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi,
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enum mtk_dpi_out_yc_map map)
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{
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u32 val;
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switch (map) {
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case MTK_DPI_OUT_YC_MAP_RGB:
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val = YC_MAP_RGB;
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break;
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case MTK_DPI_OUT_YC_MAP_CYCY:
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val = YC_MAP_CYCY;
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break;
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case MTK_DPI_OUT_YC_MAP_YCYC:
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val = YC_MAP_YCYC;
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break;
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case MTK_DPI_OUT_YC_MAP_CY:
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val = YC_MAP_CY;
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break;
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case MTK_DPI_OUT_YC_MAP_YC:
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val = YC_MAP_YC;
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break;
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default:
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val = YC_MAP_RGB;
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break;
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}
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mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK);
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}
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static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
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enum mtk_dpi_out_channel_swap swap)
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{
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u32 val;
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switch (swap) {
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case MTK_DPI_OUT_CHANNEL_SWAP_RGB:
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val = SWAP_RGB;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_GBR:
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val = SWAP_GBR;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_BRG:
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val = SWAP_BRG;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_RBG:
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val = SWAP_RBG;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_GRB:
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val = SWAP_GRB;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_BGR:
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val = SWAP_BGR;
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break;
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default:
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val = SWAP_RGB;
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break;
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}
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mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
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val << dpi->conf->channel_swap_shift,
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CH_SWAP_MASK << dpi->conf->channel_swap_shift);
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}
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static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
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{
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mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0,
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dpi->conf->yuv422_en_bit);
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}
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static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
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{
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mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0,
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dpi->conf->csc_enable_bit);
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}
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static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
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{
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mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP);
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}
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static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
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{
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mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
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}
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static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
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{
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if (dpi->conf->edge_sel_en)
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mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
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}
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static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
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enum mtk_dpi_out_color_format format)
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{
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mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
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if (format == MTK_DPI_COLOR_FORMAT_YCBCR_422) {
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mtk_dpi_config_yuv422_enable(dpi, true);
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mtk_dpi_config_csc_enable(dpi, true);
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/*
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* If height is smaller than 720, we need to use RGB_TO_BT601
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* to transfer to yuv422. Otherwise, we use RGB_TO_JPEG.
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*/
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mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <= 720 ?
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MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG,
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INT_MATRIX_SEL_MASK);
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} else {
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mtk_dpi_config_yuv422_enable(dpi, false);
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mtk_dpi_config_csc_enable(dpi, false);
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if (dpi->conf->swap_input_support)
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mtk_dpi_config_swap_input(dpi, false);
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}
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}
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static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
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{
|
|
if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
|
|
(dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) {
|
|
mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
|
|
DDR_EN | DDR_4PHASE);
|
|
mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
|
|
dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ?
|
|
EDGE_SEL : 0, EDGE_SEL);
|
|
} else {
|
|
mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
|
|
}
|
|
}
|
|
|
|
static void mtk_dpi_power_off(struct mtk_dpi *dpi)
|
|
{
|
|
if (WARN_ON(dpi->refcount == 0))
|
|
return;
|
|
|
|
if (--dpi->refcount != 0)
|
|
return;
|
|
|
|
if (dpi->pinctrl && dpi->pins_gpio)
|
|
pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
|
|
|
|
mtk_dpi_disable(dpi);
|
|
clk_disable_unprepare(dpi->pixel_clk);
|
|
clk_disable_unprepare(dpi->engine_clk);
|
|
}
|
|
|
|
static int mtk_dpi_power_on(struct mtk_dpi *dpi)
|
|
{
|
|
int ret;
|
|
|
|
if (++dpi->refcount != 1)
|
|
return 0;
|
|
|
|
ret = clk_prepare_enable(dpi->engine_clk);
|
|
if (ret) {
|
|
dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
|
|
goto err_refcount;
|
|
}
|
|
|
|
ret = clk_prepare_enable(dpi->pixel_clk);
|
|
if (ret) {
|
|
dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
|
|
goto err_pixel;
|
|
}
|
|
|
|
if (dpi->pinctrl && dpi->pins_dpi)
|
|
pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
|
|
|
|
return 0;
|
|
|
|
err_pixel:
|
|
clk_disable_unprepare(dpi->engine_clk);
|
|
err_refcount:
|
|
dpi->refcount--;
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
struct mtk_dpi_polarities dpi_pol;
|
|
struct mtk_dpi_sync_param hsync;
|
|
struct mtk_dpi_sync_param vsync_lodd = { 0 };
|
|
struct mtk_dpi_sync_param vsync_leven = { 0 };
|
|
struct mtk_dpi_sync_param vsync_rodd = { 0 };
|
|
struct mtk_dpi_sync_param vsync_reven = { 0 };
|
|
struct videomode vm = { 0 };
|
|
unsigned long pll_rate;
|
|
unsigned int factor;
|
|
|
|
/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
|
|
factor = dpi->conf->cal_factor(mode->clock);
|
|
drm_display_mode_to_videomode(mode, &vm);
|
|
pll_rate = vm.pixelclock * factor;
|
|
|
|
dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
|
|
pll_rate, vm.pixelclock);
|
|
|
|
clk_set_rate(dpi->tvd_clk, pll_rate);
|
|
pll_rate = clk_get_rate(dpi->tvd_clk);
|
|
|
|
vm.pixelclock = pll_rate / factor;
|
|
if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
|
|
(dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
|
|
clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
|
|
else
|
|
clk_set_rate(dpi->pixel_clk, vm.pixelclock);
|
|
|
|
|
|
vm.pixelclock = clk_get_rate(dpi->pixel_clk);
|
|
|
|
dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
|
|
pll_rate, vm.pixelclock);
|
|
|
|
dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
|
|
dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
|
|
dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
|
|
MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
|
|
dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
|
|
MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
|
|
hsync.sync_width = vm.hsync_len;
|
|
hsync.back_porch = vm.hback_porch;
|
|
hsync.front_porch = vm.hfront_porch;
|
|
hsync.shift_half_line = false;
|
|
vsync_lodd.sync_width = vm.vsync_len;
|
|
vsync_lodd.back_porch = vm.vback_porch;
|
|
vsync_lodd.front_porch = vm.vfront_porch;
|
|
vsync_lodd.shift_half_line = false;
|
|
|
|
if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
|
|
mode->flags & DRM_MODE_FLAG_3D_MASK) {
|
|
vsync_leven = vsync_lodd;
|
|
vsync_rodd = vsync_lodd;
|
|
vsync_reven = vsync_lodd;
|
|
vsync_leven.shift_half_line = true;
|
|
vsync_reven.shift_half_line = true;
|
|
} else if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
|
|
!(mode->flags & DRM_MODE_FLAG_3D_MASK)) {
|
|
vsync_leven = vsync_lodd;
|
|
vsync_leven.shift_half_line = true;
|
|
} else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) &&
|
|
mode->flags & DRM_MODE_FLAG_3D_MASK) {
|
|
vsync_rodd = vsync_lodd;
|
|
}
|
|
mtk_dpi_sw_reset(dpi, true);
|
|
mtk_dpi_config_pol(dpi, &dpi_pol);
|
|
|
|
mtk_dpi_config_hsync(dpi, &hsync);
|
|
mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
|
|
mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
|
|
mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
|
|
mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
|
|
|
|
mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
|
|
mtk_dpi_config_interface(dpi, !!(vm.flags &
|
|
DISPLAY_FLAGS_INTERLACED));
|
|
if (vm.flags & DISPLAY_FLAGS_INTERLACED)
|
|
mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1);
|
|
else
|
|
mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
|
|
|
|
mtk_dpi_config_channel_limit(dpi);
|
|
mtk_dpi_config_bit_num(dpi, dpi->bit_num);
|
|
mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
|
|
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
|
|
mtk_dpi_config_color_format(dpi, dpi->color_format);
|
|
mtk_dpi_config_2n_h_fre(dpi);
|
|
mtk_dpi_dual_edge(dpi);
|
|
mtk_dpi_config_disable_edge(dpi);
|
|
mtk_dpi_sw_reset(dpi, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
|
|
struct drm_bridge_state *bridge_state,
|
|
struct drm_crtc_state *crtc_state,
|
|
struct drm_connector_state *conn_state,
|
|
unsigned int *num_output_fmts)
|
|
{
|
|
struct mtk_dpi *dpi = bridge_to_dpi(bridge);
|
|
u32 *output_fmts;
|
|
|
|
*num_output_fmts = 0;
|
|
|
|
if (!dpi->conf->output_fmts) {
|
|
dev_err(dpi->dev, "output_fmts should not be null\n");
|
|
return NULL;
|
|
}
|
|
|
|
output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts),
|
|
GFP_KERNEL);
|
|
if (!output_fmts)
|
|
return NULL;
|
|
|
|
*num_output_fmts = dpi->conf->num_output_fmts;
|
|
|
|
memcpy(output_fmts, dpi->conf->output_fmts,
|
|
sizeof(*output_fmts) * dpi->conf->num_output_fmts);
|
|
|
|
return output_fmts;
|
|
}
|
|
|
|
static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
|
|
struct drm_bridge_state *bridge_state,
|
|
struct drm_crtc_state *crtc_state,
|
|
struct drm_connector_state *conn_state,
|
|
u32 output_fmt,
|
|
unsigned int *num_input_fmts)
|
|
{
|
|
u32 *input_fmts;
|
|
|
|
*num_input_fmts = 0;
|
|
|
|
input_fmts = kcalloc(1, sizeof(*input_fmts),
|
|
GFP_KERNEL);
|
|
if (!input_fmts)
|
|
return NULL;
|
|
|
|
*num_input_fmts = 1;
|
|
input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
|
|
|
|
return input_fmts;
|
|
}
|
|
|
|
static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
|
|
struct drm_bridge_state *bridge_state,
|
|
struct drm_crtc_state *crtc_state,
|
|
struct drm_connector_state *conn_state)
|
|
{
|
|
struct mtk_dpi *dpi = bridge_to_dpi(bridge);
|
|
unsigned int out_bus_format;
|
|
|
|
out_bus_format = bridge_state->output_bus_cfg.format;
|
|
|
|
if (out_bus_format == MEDIA_BUS_FMT_FIXED)
|
|
if (dpi->conf->num_output_fmts)
|
|
out_bus_format = dpi->conf->output_fmts[0];
|
|
|
|
dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
|
|
bridge_state->input_bus_cfg.format,
|
|
bridge_state->output_bus_cfg.format);
|
|
|
|
dpi->output_fmt = out_bus_format;
|
|
dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
|
|
dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
|
|
dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
|
|
if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
|
|
dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422;
|
|
else
|
|
dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
|
|
enum drm_bridge_attach_flags flags)
|
|
{
|
|
struct mtk_dpi *dpi = bridge_to_dpi(bridge);
|
|
|
|
return drm_bridge_attach(bridge->encoder, dpi->next_bridge,
|
|
&dpi->bridge, flags);
|
|
}
|
|
|
|
static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge,
|
|
const struct drm_display_mode *mode,
|
|
const struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct mtk_dpi *dpi = bridge_to_dpi(bridge);
|
|
|
|
drm_mode_copy(&dpi->mode, adjusted_mode);
|
|
}
|
|
|
|
static void mtk_dpi_bridge_disable(struct drm_bridge *bridge)
|
|
{
|
|
struct mtk_dpi *dpi = bridge_to_dpi(bridge);
|
|
|
|
mtk_dpi_power_off(dpi);
|
|
}
|
|
|
|
static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
|
|
{
|
|
struct mtk_dpi *dpi = bridge_to_dpi(bridge);
|
|
|
|
mtk_dpi_power_on(dpi);
|
|
mtk_dpi_set_display_mode(dpi, &dpi->mode);
|
|
mtk_dpi_enable(dpi);
|
|
}
|
|
|
|
static enum drm_mode_status
|
|
mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
|
|
const struct drm_display_info *info,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
struct mtk_dpi *dpi = bridge_to_dpi(bridge);
|
|
|
|
if (mode->clock > dpi->conf->max_clock_khz)
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
|
|
.attach = mtk_dpi_bridge_attach,
|
|
.mode_set = mtk_dpi_bridge_mode_set,
|
|
.mode_valid = mtk_dpi_bridge_mode_valid,
|
|
.disable = mtk_dpi_bridge_disable,
|
|
.enable = mtk_dpi_bridge_enable,
|
|
.atomic_check = mtk_dpi_bridge_atomic_check,
|
|
.atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts,
|
|
.atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts,
|
|
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
|
|
.atomic_reset = drm_atomic_helper_bridge_reset,
|
|
};
|
|
|
|
void mtk_dpi_start(struct device *dev)
|
|
{
|
|
struct mtk_dpi *dpi = dev_get_drvdata(dev);
|
|
|
|
mtk_dpi_power_on(dpi);
|
|
}
|
|
|
|
void mtk_dpi_stop(struct device *dev)
|
|
{
|
|
struct mtk_dpi *dpi = dev_get_drvdata(dev);
|
|
|
|
mtk_dpi_power_off(dpi);
|
|
}
|
|
|
|
static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct mtk_dpi *dpi = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = data;
|
|
int ret;
|
|
|
|
ret = drm_simple_encoder_init(drm_dev, &dpi->encoder,
|
|
DRM_MODE_ENCODER_TMDS);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize decoder: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev);
|
|
|
|
ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL,
|
|
DRM_BRIDGE_ATTACH_NO_CONNECTOR);
|
|
if (ret)
|
|
goto err_cleanup;
|
|
|
|
dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder);
|
|
if (IS_ERR(dpi->connector)) {
|
|
dev_err(dev, "Unable to create bridge connector\n");
|
|
ret = PTR_ERR(dpi->connector);
|
|
goto err_cleanup;
|
|
}
|
|
drm_connector_attach_encoder(dpi->connector, &dpi->encoder);
|
|
|
|
return 0;
|
|
|
|
err_cleanup:
|
|
drm_encoder_cleanup(&dpi->encoder);
|
|
return ret;
|
|
}
|
|
|
|
static void mtk_dpi_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct mtk_dpi *dpi = dev_get_drvdata(dev);
|
|
|
|
drm_encoder_cleanup(&dpi->encoder);
|
|
}
|
|
|
|
static const struct component_ops mtk_dpi_component_ops = {
|
|
.bind = mtk_dpi_bind,
|
|
.unbind = mtk_dpi_unbind,
|
|
};
|
|
|
|
static unsigned int mt8173_calculate_factor(int clock)
|
|
{
|
|
if (clock <= 27000)
|
|
return 3 << 4;
|
|
else if (clock <= 84000)
|
|
return 3 << 3;
|
|
else if (clock <= 167000)
|
|
return 3 << 2;
|
|
else
|
|
return 3 << 1;
|
|
}
|
|
|
|
static unsigned int mt2701_calculate_factor(int clock)
|
|
{
|
|
if (clock <= 64000)
|
|
return 4;
|
|
else if (clock <= 128000)
|
|
return 2;
|
|
else
|
|
return 1;
|
|
}
|
|
|
|
static unsigned int mt8183_calculate_factor(int clock)
|
|
{
|
|
if (clock <= 27000)
|
|
return 8;
|
|
else if (clock <= 167000)
|
|
return 4;
|
|
else
|
|
return 2;
|
|
}
|
|
|
|
static const u32 mt8173_output_fmts[] = {
|
|
MEDIA_BUS_FMT_RGB888_1X24,
|
|
};
|
|
|
|
static const u32 mt8183_output_fmts[] = {
|
|
MEDIA_BUS_FMT_RGB888_2X12_LE,
|
|
MEDIA_BUS_FMT_RGB888_2X12_BE,
|
|
};
|
|
|
|
static const struct mtk_dpi_conf mt8173_conf = {
|
|
.cal_factor = mt8173_calculate_factor,
|
|
.reg_h_fre_con = 0xe0,
|
|
.max_clock_khz = 300000,
|
|
.output_fmts = mt8173_output_fmts,
|
|
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
|
|
.is_ck_de_pol = true,
|
|
.swap_input_support = true,
|
|
.dimension_mask = HPW_MASK,
|
|
.hvsize_mask = HSIZE_MASK,
|
|
.channel_swap_shift = CH_SWAP,
|
|
.yuv422_en_bit = YUV422_EN,
|
|
.csc_enable_bit = CSC_ENABLE,
|
|
};
|
|
|
|
static const struct mtk_dpi_conf mt2701_conf = {
|
|
.cal_factor = mt2701_calculate_factor,
|
|
.reg_h_fre_con = 0xb0,
|
|
.edge_sel_en = true,
|
|
.max_clock_khz = 150000,
|
|
.output_fmts = mt8173_output_fmts,
|
|
.num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
|
|
.is_ck_de_pol = true,
|
|
.swap_input_support = true,
|
|
.dimension_mask = HPW_MASK,
|
|
.hvsize_mask = HSIZE_MASK,
|
|
.channel_swap_shift = CH_SWAP,
|
|
.yuv422_en_bit = YUV422_EN,
|
|
.csc_enable_bit = CSC_ENABLE,
|
|
};
|
|
|
|
static const struct mtk_dpi_conf mt8183_conf = {
|
|
.cal_factor = mt8183_calculate_factor,
|
|
.reg_h_fre_con = 0xe0,
|
|
.max_clock_khz = 100000,
|
|
.output_fmts = mt8183_output_fmts,
|
|
.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
|
|
.is_ck_de_pol = true,
|
|
.swap_input_support = true,
|
|
.dimension_mask = HPW_MASK,
|
|
.hvsize_mask = HSIZE_MASK,
|
|
.channel_swap_shift = CH_SWAP,
|
|
.yuv422_en_bit = YUV422_EN,
|
|
.csc_enable_bit = CSC_ENABLE,
|
|
};
|
|
|
|
static const struct mtk_dpi_conf mt8192_conf = {
|
|
.cal_factor = mt8183_calculate_factor,
|
|
.reg_h_fre_con = 0xe0,
|
|
.max_clock_khz = 150000,
|
|
.output_fmts = mt8183_output_fmts,
|
|
.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
|
|
.is_ck_de_pol = true,
|
|
.swap_input_support = true,
|
|
.dimension_mask = HPW_MASK,
|
|
.hvsize_mask = HSIZE_MASK,
|
|
.channel_swap_shift = CH_SWAP,
|
|
.yuv422_en_bit = YUV422_EN,
|
|
.csc_enable_bit = CSC_ENABLE,
|
|
};
|
|
|
|
static int mtk_dpi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct mtk_dpi *dpi;
|
|
struct resource *mem;
|
|
int ret;
|
|
|
|
dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
|
|
if (!dpi)
|
|
return -ENOMEM;
|
|
|
|
dpi->dev = dev;
|
|
dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
|
|
dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
|
|
|
|
dpi->pinctrl = devm_pinctrl_get(&pdev->dev);
|
|
if (IS_ERR(dpi->pinctrl)) {
|
|
dpi->pinctrl = NULL;
|
|
dev_dbg(&pdev->dev, "Cannot find pinctrl!\n");
|
|
}
|
|
if (dpi->pinctrl) {
|
|
dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep");
|
|
if (IS_ERR(dpi->pins_gpio)) {
|
|
dpi->pins_gpio = NULL;
|
|
dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n");
|
|
}
|
|
if (dpi->pins_gpio)
|
|
pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
|
|
|
|
dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default");
|
|
if (IS_ERR(dpi->pins_dpi)) {
|
|
dpi->pins_dpi = NULL;
|
|
dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n");
|
|
}
|
|
}
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
dpi->regs = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(dpi->regs)) {
|
|
ret = PTR_ERR(dpi->regs);
|
|
dev_err(dev, "Failed to ioremap mem resource: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
dpi->engine_clk = devm_clk_get(dev, "engine");
|
|
if (IS_ERR(dpi->engine_clk)) {
|
|
ret = PTR_ERR(dpi->engine_clk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "Failed to get engine clock: %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
dpi->pixel_clk = devm_clk_get(dev, "pixel");
|
|
if (IS_ERR(dpi->pixel_clk)) {
|
|
ret = PTR_ERR(dpi->pixel_clk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "Failed to get pixel clock: %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
dpi->tvd_clk = devm_clk_get(dev, "pll");
|
|
if (IS_ERR(dpi->tvd_clk)) {
|
|
ret = PTR_ERR(dpi->tvd_clk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
dpi->irq = platform_get_irq(pdev, 0);
|
|
if (dpi->irq <= 0)
|
|
return -EINVAL;
|
|
|
|
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
|
|
NULL, &dpi->next_bridge);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node);
|
|
|
|
platform_set_drvdata(pdev, dpi);
|
|
|
|
dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
|
|
dpi->bridge.of_node = dev->of_node;
|
|
dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
|
|
|
|
drm_bridge_add(&dpi->bridge);
|
|
|
|
ret = component_add(dev, &mtk_dpi_component_ops);
|
|
if (ret) {
|
|
drm_bridge_remove(&dpi->bridge);
|
|
dev_err(dev, "Failed to add component: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_dpi_remove(struct platform_device *pdev)
|
|
{
|
|
struct mtk_dpi *dpi = platform_get_drvdata(pdev);
|
|
|
|
component_del(&pdev->dev, &mtk_dpi_component_ops);
|
|
drm_bridge_remove(&dpi->bridge);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mtk_dpi_of_ids[] = {
|
|
{ .compatible = "mediatek,mt2701-dpi",
|
|
.data = &mt2701_conf,
|
|
},
|
|
{ .compatible = "mediatek,mt8173-dpi",
|
|
.data = &mt8173_conf,
|
|
},
|
|
{ .compatible = "mediatek,mt8183-dpi",
|
|
.data = &mt8183_conf,
|
|
},
|
|
{ .compatible = "mediatek,mt8192-dpi",
|
|
.data = &mt8192_conf,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
|
|
|
|
struct platform_driver mtk_dpi_driver = {
|
|
.probe = mtk_dpi_probe,
|
|
.remove = mtk_dpi_remove,
|
|
.driver = {
|
|
.name = "mediatek-dpi",
|
|
.of_match_table = mtk_dpi_of_ids,
|
|
},
|
|
};
|