ba3ae6a1d4
This patch provides an alternative mean to support memory above 16MiB (128Mib) by replacing 3byte address op codes by their associated 4byte address versions. Using the dedicated 4byte address op codes doesn't change the internal state of the SPI NOR memory as opposed to using other means such as updating a Base Address Register (BAR) and sending command to enter/leave the 4byte mode. Hence when a CPU reset occurs, early bootloaders don't need to be aware of BAR value or 4byte mode being enabled: they can still access the first 16MiB of the SPI NOR memory using the regular 3byte address op codes. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Tested-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> |
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| .. | ||
| aspeed-smc.c | ||
| atmel-quadspi.c | ||
| cadence-quadspi.c | ||
| fsl-quadspi.c | ||
| hisi-sfc.c | ||
| Kconfig | ||
| Makefile | ||
| mtk-quadspi.c | ||
| nxp-spifi.c | ||
| spi-nor.c | ||