Alexey Brodkin e2fc61f384 ARCv2: [axs103] bump CPU frequency from 75 to 90 MHZ ...

With up-to-date FPGA builds ARC cores are supposed to correctly operate
even with 90 MHz clock (which is a target frequency for AXS103 release).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: arc-linux-dev@synopsys.com

2015-07-09 17:36:31 +05:30

..

abilis_tb10x.dtsi

dmaengine: dw: define DW_DMA_MAX_NR_MASTERS

2015-02-04 22:39:44 -08:00

abilis_tb100_dvk.dts

ARC: [TB10x] Updates for GPIO and pinctrl

2013-11-11 09:57:44 +05:30

abilis_tb100.dtsi

ARC: [TB10x] Updates for GPIO and pinctrl

2013-11-11 09:57:44 +05:30

abilis_tb101_dvk.dts

ARC: [TB10x] Updates for GPIO and pinctrl

2013-11-11 09:57:44 +05:30

abilis_tb101.dtsi

ARC: [TB10x] Updates for GPIO and pinctrl

2013-11-11 09:57:44 +05:30

axc001.dtsi

ARC: [axs101] Prepare for AXS103

2015-06-25 06:00:20 +05:30

axc003_idu.dtsi

ARCv2: [axs103] bump CPU frequency from 75 to 90 MHZ

2015-07-09 17:36:31 +05:30

axc003.dtsi

ARCv2: [axs103] bump CPU frequency from 75 to 90 MHZ

2015-07-09 17:36:31 +05:30

axs10x_mb.dtsi

ARC: [axs101] Prepare for AXS103

2015-06-25 06:00:20 +05:30

axs101.dts

ARC: [axs101] support early 8250 uart

2015-06-19 18:09:30 +05:30

axs103_idu.dts

ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores

2015-06-25 06:00:20 +05:30

axs103.dts

ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores

2015-06-25 06:00:20 +05:30

Makefile

ARC: [plat_arcfpga]->[plat_sim]

2015-06-19 18:09:26 +05:30

nsim_700.dts

ARC: [plat_arcfpga]->[plat_sim]

2015-06-19 18:09:26 +05:30

nsim_hs_idu.dts

ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores

2015-06-25 06:00:19 +05:30

nsim_hs.dts

ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores

2015-06-25 06:00:19 +05:30

nsimosci_hs_idu.dts

ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores

2015-06-25 06:00:19 +05:30

nsimosci_hs.dts

ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores

2015-06-25 06:00:19 +05:30

nsimosci.dts

ARC: [nsimosci] move peripherals to match model to FPGA

2014-12-15 11:24:58 +05:30

skeleton.dtsi

ARC: [plat-arcfpga]: Enabling DeviceTree for Angel4 board

2013-02-15 23:15:57 +05:30

vdk_axc003_idu.dtsi

ARCv2: [vdk] dts files and defconfig for HS38 VDK

2015-06-25 06:00:21 +05:30

vdk_axc003.dtsi

ARCv2: [vdk] dts files and defconfig for HS38 VDK

2015-06-25 06:00:21 +05:30

vdk_axs10x_mb.dtsi

ARCv2: [vdk] dts files and defconfig for HS38 VDK

2015-06-25 06:00:21 +05:30

vdk_hs38_smp.dts

ARCv2: [vdk] dts files and defconfig for HS38 VDK

2015-06-25 06:00:21 +05:30

vdk_hs38.dts

ARCv2: [vdk] dts files and defconfig for HS38 VDK

2015-06-25 06:00:21 +05:30