bb2b2624db
Some of i.MX8M SoCs have MU clock, they need to be managed in runtime to make sure the MU clock can be off in runtime, add runtime PM callback to handle MU clock. And on i.MX8MP, the MU clock is combined with power domain and runtime PM is enabled for the clock driver, during noirq suspend/resume phase, runtime PM is disabled by device suspend, but the MU context save/restore needs to enable MU clock for register access, calling clock prepare/enable will trigger runtime resume failure and lead to system suspend failed. Actually, the MU context save/restore is ONLY necessary for SCU IPC MU, other MUs especially on i.MX8MP platforms which have MU clock assigned, they need to runtime request/free mailbox channel in the consumer driver, so no need to save/restore MU context for them, hence it can avoid this issue, so the MU context save/restore is ONLY applied to i.MX platforms MU instance without clock present. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> |
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arm_mhu.c | ||
armada-37xx-rwtm-mailbox.c | ||
bcm2835-mailbox.c | ||
bcm-flexrm-mailbox.c | ||
bcm-pdc-mailbox.c | ||
hi3660-mailbox.c | ||
hi6220-mailbox.c | ||
imx-mailbox.c | ||
Kconfig | ||
mailbox-altera.c | ||
mailbox-sti.c | ||
mailbox-test.c | ||
mailbox-xgene-slimpro.c | ||
mailbox.c | ||
mailbox.h | ||
Makefile | ||
mtk-cmdq-mailbox.c | ||
omap-mailbox.c | ||
pcc.c | ||
pl320-ipc.c | ||
platform_mhu.c | ||
qcom-apcs-ipc-mailbox.c | ||
qcom-ipcc.c | ||
rockchip-mailbox.c | ||
sprd-mailbox.c | ||
stm32-ipcc.c | ||
sun6i-msgbox.c | ||
tegra-hsp.c | ||
ti-msgmgr.c | ||
zynqmp-ipi-mailbox.c |