bb34b4c8cf
This patch adds entries min_efuse_value, max_efuse_value, default_temp_offset, trigger_type, cal_type, trim_first_point, trim_second_point, max_trigger_level trigger_enable in the TMU platform data structure. Also the driver is modified to use the data passed by these new platform memebers instead of the constant macros. All these changes helps in separating the SOC specific data part from the TMU driver. Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Acked-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* exynos_tmu_data.c - Samsung EXYNOS tmu data file
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*
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* Copyright (C) 2013 Samsung Electronics
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include "exynos_thermal_common.h"
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#include "exynos_tmu.h"
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#include "exynos_tmu_data.h"
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#if defined(CONFIG_CPU_EXYNOS4210)
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struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
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.threshold = 80,
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.trigger_levels[0] = 5,
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.trigger_levels[1] = 20,
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.trigger_levels[2] = 30,
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.trigger_enable[0] = true,
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.trigger_enable[1] = true,
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.trigger_enable[2] = true,
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.trigger_enable[3] = false,
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.trigger_type[0] = THROTTLE_ACTIVE,
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.trigger_type[1] = THROTTLE_ACTIVE,
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.trigger_type[2] = SW_TRIP,
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.max_trigger_level = 4,
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.gain = 15,
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.reference_voltage = 7,
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.cal_type = TYPE_ONE_POINT_TRIMMING,
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.min_efuse_value = 40,
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.max_efuse_value = 100,
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.first_point_trim = 25,
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.second_point_trim = 85,
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.default_temp_offset = 50,
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.freq_tab[0] = {
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.freq_clip_max = 800 * 1000,
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.temp_level = 85,
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},
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.freq_tab[1] = {
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.freq_clip_max = 200 * 1000,
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.temp_level = 100,
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},
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.freq_tab_count = 2,
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.type = SOC_ARCH_EXYNOS4210,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
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struct exynos_tmu_platform_data const exynos5250_default_tmu_data = {
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.threshold_falling = 10,
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.trigger_levels[0] = 85,
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.trigger_levels[1] = 103,
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.trigger_levels[2] = 110,
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.trigger_enable[0] = true,
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.trigger_enable[1] = true,
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.trigger_enable[2] = true,
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.trigger_enable[3] = false,
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.trigger_type[0] = THROTTLE_ACTIVE,
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.trigger_type[1] = THROTTLE_ACTIVE,
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.trigger_type[2] = SW_TRIP,
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.max_trigger_level = 4,
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.gain = 8,
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.reference_voltage = 16,
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.noise_cancel_mode = 4,
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.cal_type = TYPE_ONE_POINT_TRIMMING,
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.efuse_value = 55,
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.min_efuse_value = 40,
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.max_efuse_value = 100,
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.first_point_trim = 25,
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.second_point_trim = 85,
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.default_temp_offset = 50,
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.freq_tab[0] = {
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.freq_clip_max = 800 * 1000,
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.temp_level = 85,
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},
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.freq_tab[1] = {
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.freq_clip_max = 200 * 1000,
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.temp_level = 103,
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},
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.freq_tab_count = 2,
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.type = SOC_ARCH_EXYNOS,
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};
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#endif
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