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linux/drivers/clk/rockchip
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Stephen Boyd 9bb87c027c The biggest addition is probably the special clock-type for ddr clock 
control. While reading that clock is done the normal way from the
 registers, setting it always requires some sort of special handling
 to let the system survive this addition.
 
 As the commit message explains, there are currently 3 handling-types
 known. General SRAM-based code on rk3288 and before (which is waiting
 essentially for the PIE support that is currently being worked on),
 SCPI-based clk setting on the rk3368 through a coprocessor, which we
 might support once the support for legacy scpi-variants has matured
 and now on the rk3399 (and probably later) using a dcf controller that
 is controlled from the arm-trusted-firmware and gets accessed through
 firmware calls from the kernel. This is the variant we currently
 support, but the clock type is made to support the other variants in
 the future as well.
 
 Apart from that slightly bigger chunk, we have a mix of PLL rates,
 clock-ids and flags mainly for the rk3399.
 
 And interestingly an iomap fix for the legacy gate driver, where I
 hopefully could deter the submitter from actually using that in any
 new works.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJXzrz5AAoJEPOmecmc0R2B0NMH/0SGrQnrUsaq0cvjZPaq8jTD
 nJDVIRw099HNM3QZCfy+FZbSsnmex93clX+Fn4UdehplrCZ8ExX1wpPkMwvFcPJF
 M34YyFXx5MU9OmDsJXd1UlGRD/mH0L6hKnmfBQiPbK33ObXbr7LCC1L3go+oYABN
 eHaOzO1KIcdoCQd6RlVAQHCsiDy8akUJ68P2uACHZ7VVgvGw2f3NdJhOKTD5lCuf
 WH/MRo9X9bPDGHpFJIX+mZzZgYsMqUjyF/mYU/VMoH70w+YZTnfcbrYpJ0VkgBYd
 aQF2B9VXhed9EQG3Gfu+jgsWoWLed9AJf83UP6eMsPTPLNQBqgzoDZwylbY1Szk=
 =LjDG
 -----END PGP SIGNATURE-----

Merge tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

The biggest addition is probably the special clock-type for ddr clock
control. While reading that clock is done the normal way from the
registers, setting it always requires some sort of special handling
to let the system survive this addition.

As the commit message explains, there are currently 3 handling-types
known. General SRAM-based code on rk3288 and before (which is waiting
essentially for the PIE support that is currently being worked on),
SCPI-based clk setting on the rk3368 through a coprocessor, which we
might support once the support for legacy scpi-variants has matured
and now on the rk3399 (and probably later) using a dcf controller that
is controlled from the arm-trusted-firmware and gets accessed through
firmware calls from the kernel. This is the variant we currently
support, but the clock type is made to support the other variants in
the future as well.

Apart from that slightly bigger chunk, we have a mix of PLL rates,
clock-ids and flags mainly for the rk3399.

And interestingly an iomap fix for the legacy gate driver, where I
hopefully could deter the submitter from actually using that in any
new works.

* tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: use the dclk_vop_frac clock ids on rk3399
  clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers
  clk: rockchip: add 2016M to big cpu clk rate table on rk3399
  clk: rockchip: add rk3399 ddr clock support
  clk: rockchip: add dclk_vop_frac ids for rk3399 vop
  clk: rockchip: add new clock-type for the ddrclk
  soc: rockchip: add header for ddr rate SIP interface
  clk: rockchip: add SCLK_DDRC id for rk3399 ddrc
  clk: rockchip: handle of_iomap failures in legacy clock driver
  clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical
  clk: rockchip: use general clock flag when registering pll
  clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399
  clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
2016-09-06 18:12:24 -07:00
..
clk-cpu.c clk: rockchip: fix cpuclk registration error handling 2016-05-30 09:40:23 +02:00
clk-ddr.c clk: rockchip: add new clock-type for the ddrclk 2016-09-01 11:23:56 +02:00
clk-inverter.c clk: rockchip: don't return NULL when registering inverter fails 2016-02-15 23:35:20 +01:00
clk-mmc-phase.c clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization" 2016-05-30 09:40:23 +02:00
clk-pll.c clk: rockchip: use general clock flag when registering pll 2016-08-08 10:57:21 +02:00
clk-rk3036.c clk: rockchip: release io resource when failing to init clk 2016-03-27 13:03:35 +02:00
clk-rk3188.c clk: rockchip: release io resource when failing to init clk 2016-03-27 13:03:35 +02:00
clk-rk3228.c clk: rockchip: export rk3228 MAC clocks 2016-07-01 01:50:11 +02:00
clk-rk3288.c clk: rockchip: release io resource when failing to init clk 2016-03-27 13:03:35 +02:00
clk-rk3368.c clk: rockchip: release io resource when failing to init clk 2016-03-27 13:03:35 +02:00
clk-rk3399.c The biggest addition is probably the special clock-type for ddr clock 2016-09-06 18:12:24 -07:00
clk-rockchip.c clk: rockchip: handle of_iomap failures in legacy clock driver 2016-08-23 18:00:25 +02:00
clk.c clk: rockchip: add new clock-type for the ddrclk 2016-09-01 11:23:56 +02:00
clk.h clk: rockchip: add new clock-type for the ddrclk 2016-09-01 11:23:56 +02:00
Makefile clk: rockchip: add new clock-type for the ddrclk 2016-09-01 11:23:56 +02:00
softrst.c clk: rockchip: Make reset_control_ops const 2016-03-29 16:29:46 -07:00