438d3fc46f
Keystone clock controller bindings were marked as work-in-progress /
unstable in 2013 in commit b9e0d40c0d83 ("clk: keystone: add Keystone
PLL clock driver") and commit 7affe5685c96 ("clk: keystone: Add gate
control clock driver") Almost eleven years is enough, so drop the
"unstable" remark and expect usual ABI rules.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240224091236.10146-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
28 lines
889 B
Plaintext
28 lines
889 B
Plaintext
Binding for Keystone gate control driver which uses PSC controller IP.
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be "ti,keystone,psc-clock".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : parent clock phandle
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- reg : psc control and domain address address space
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- reg-names : psc control and domain registers
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- domain-id : psc domain id needed to check the transition state register
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Optional properties:
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- clock-output-names : From common clock binding to override the
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default output clock name
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Example:
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clkusb: clkusb {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk16>;
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clock-output-names = "usb";
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reg = <0x02350008 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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