79d770afa0
Drop common properties already defined in referenced common Qualcomm SoC TLMM bindings and use "unevaluatedProperties: false". This makes the binding smaller and easier to review. In few places move the "required:" block to bottom, to match convention. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208215534.195854-9-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
138 lines
4.5 KiB
YAML
138 lines
4.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. X1E80100 TLMM block
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maintainers:
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- Rajendra Nayak <quic_rjendra@quicinc.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm X1E80100 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,x1e80100-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 119
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gpio-line-names:
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maxItems: 238
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-x1e80100-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-x1e80100-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-x1e80100-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aon_cci, aoss_cti, atest_char, atest_char0,
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atest_char1, atest_char2, atest_char3, atest_usb,
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audio_ext, audio_ref, cam_aon, cam_mclk, cci_async,
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cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
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cci_timer4, cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3,
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cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
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ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6, ddr_pxi7,
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edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, eusb0_ac, eusb1_ac,
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eusb2_ac, eusb3_ac, eusb5_ac, eusb6_ac, gcc_gp1, gcc_gp2,
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gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0,
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i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, mdp_vsync0,
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mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5,
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mdp_vsync6, mdp_vsync7, mdp_vsync8, pcie3_clk, pcie4_clk,
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pcie5_clk, pcie6a_clk, pcie6b_clk, phase_flag, pll_bist, pll_clk,
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prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
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qdss_gpio, qspi00, qspi01, qspi02, qspi03, qspi0_clk, qspi0_cs0,
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qspi0_cs1, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
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qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
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qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2,
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qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, sd_write, sdc4_clk,
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sdc4_cmd, sdc4_data0, sdc4_data1, sdc4_data2, sdc4_data3, sys_throttle,
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tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5,
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tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
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tsense_pwm1, tsense_pwm2, sense_pwm3, tsense_pwm4, usb0_dp, usb0_phy,
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usb0_sbrx, usb0_sbtx, usb1_dp, usb1_phy, usb1_sbrx, usb1_sbtx,
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usb2_dp, usb2_phy, usb2_sbrx, usb2_sbtx, vsense_trigger ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,x1e80100-tlmm";
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reg = <0x0f100000 0xf00000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 239>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-state {
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rx-pins {
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pins = "gpio26";
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function = "qup2_se7";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio27";
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function = "qup2_se7";
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bias-disable;
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};
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};
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};
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...
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