linux/include/drm/drm_hdcp.h
Linus Torvalds 851ca779d1 drm next pull request for 5.1
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Merge tag 'drm-next-2019-03-06' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "This is the main drm pull request for the 5.1 merge window.

  The big changes I'd highlight are:
   - nouveau has HMM support now, there is finally an in-tree user so we
     can quieten down the rip it out people.
   - i915 now enables fastboot by default on Skylake+
   - Displayport Multistream support has been refactored and should
     hopefully be more reliable.

  Core:
   - header cleanups aiming towards removing drmP.h
   - dma-buf fence seqnos to 64-bits
   - common helper for DP mst hotplug for radeon,i915,amdgpu + new
     refcounting scheme
   - MST i2c improvements
   - drm_syncobj_cb removal
   - ARM FB compression fourcc
   - P010 + P016 fourcc
   - allwinner tiled format modifier
   - i2c over aux I2C_M_STOP support
   - DRM_AUTH handling fixes

  TTM:
   - ref/unref renaming

  New driver:
   - ARM komeda display driver

  scheduler:
   - refactor mirror list handling
   - rework hw fence processing
   - 0 run queue entity fix

  bridge:
   - TI DS90C185 LVDS bridge
   - thc631lvdm83d bridge improvements
   - cadence + allwinner DSI ported to generic phy

  panels:
   - Sitronix ST7701 panel
   - Kingdisplay KD097D04
   - LeMaker BL035-RGB-002
   - PDA 91-00156-A0
   - Innolux EE101IA-01D

  i915:
   - Enable fastboot by default on SKL+/VLV/CHV
   - Export RPCS configuration for ICL media driver
   - Coffelake PCI ID
   - CNL clocks setup fixes
   - ACPI/PMIC support for MIPI/DSI
   - Per-engine WA init for all engines
   - Shrinker locking fixes
   - Kerneldoc updates
   - Lots of ring improvements and reset fixes
   - Coffeelake GVT Support
   - VFIO GVT EDID Region support
   - runtime PM wakeref tracking
   - ILK->IVB primary plane enable delays
   - userptr mutex locking fixes
   - DSI fixes
   - LVDS/TV cleanups
   - HW readout fixes
   - LUT robustness fixes
   - ICL display and watermark fixes
   - gem mmap race fix

  amdgpu:
   - add scheduled dependencies interface
   - DCC on scanout surfaces
   - vega10/20 BACO support
   - Multiple IH rings on soc15
   - XGMI locking fixes
   - DC i2c/aux cleanups
   - runtime SMU debug interface
   - Kexec improvmeents
   - SR-IOV fixes
   - DC freesync + ABM fixes
   - GDS fixes
   - GPUVM fixes
   - vega20 PCIE DPM switching fixes
   - Context priority handling fixes

  radeon:
   - fix missing break in evergreen parser

  nouveau:
   - SVM support via HMM

  msm:
   - QCOM Compressed modifier support

  exynos:
   - s5pv210 rotator support

  imx:
   - zpos property support
   - pending update fixes

  v3d:
   - cache flush improvments

  vc4:
   - reflection support
   - HDMI overscan support

  tegra:
   - CEC refactoring
   - HDMI audio fixes
   - Tegra186 prep work
   - SOR crossbar device tree fixes

  sun4i:
   - implicit fencing support
   - YUV and scalar support improvements
   - A23 support
   - tiling fixes

  atmel-hlcdc:
   - clipping and rotation property fixes

  qxl:
   - BO and PRIME improvements
   - generic fbdev emulation

  dw-hdmi:
   - HDMI 2.0 2160p
   - YUV420 ouput

  rockchip:
   - implicit fencing support
   - reflection proerties

  virtio-gpu:
   - use generic fbdev emulation

  tilcdc:
   - cpufreq vs crtc init fix

  rcar-du:
   - R8A774C0 support
   - D3/E3 RGB output routing fixes and DPAD0 support
   - RA87744 LVDS support

  bochs:
   - atomic and generic fbdev emulation
   - ID mismatch error on bochs load

  meson:
   - remove firmware fbs"

* tag 'drm-next-2019-03-06' of git://anongit.freedesktop.org/drm/drm: (1130 commits)
  drm/amd/display: Use vrr friendly pageflip throttling in DC.
  drm/imx: only send commit done event when all state has been applied
  drm/imx: allow building under COMPILE_TEST
  drm/imx: imx-tve: depend on COMMON_CLK
  drm/imx: ipuv3-plane: add zpos property
  drm/imx: ipuv3-plane: add function to query atomic update status
  gpu: ipu-v3: prg: add function to get channel configure status
  gpu: ipu-v3: pre: add double buffer status readback
  drm/amdgpu: Bump amdgpu version for context priority override.
  drm/amdgpu/powerplay: fix typo in BACO header guards
  drm/amdgpu/powerplay: fix return codes in BACO code
  drm/amdgpu: add missing license on baco files
  drm/bochs: Fix the ID mismatch error
  drm/nouveau/dmem: use dma addresses during migration copies
  drm/nouveau/dmem: use physical vram addresses during migration copies
  drm/nouveau/dmem: extend copy function to allow direct use of physical addresses
  drm/nouveau/svm: new ioctl to migrate process memory to GPU memory
  drm/nouveau/dmem: device memory helpers for SVM
  drm/nouveau/svm: initial support for shared virtual memory
  drm/nouveau: prepare for enabling svm with existing userspace interfaces
  ...
2019-03-08 08:23:15 -08:00

274 lines
7.6 KiB
C

/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2017 Google, Inc.
*
* Authors:
* Sean Paul <seanpaul@chromium.org>
*/
#ifndef _DRM_HDCP_H_INCLUDED_
#define _DRM_HDCP_H_INCLUDED_
#include <linux/types.h>
/* Period of hdcp checks (to ensure we're still authenticated) */
#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
/* Shared lengths/masks between HDMI/DVI/DisplayPort */
#define DRM_HDCP_AN_LEN 8
#define DRM_HDCP_BSTATUS_LEN 2
#define DRM_HDCP_KSV_LEN 5
#define DRM_HDCP_RI_LEN 2
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
/* Slave address for the HDCP registers in the receiver */
#define DRM_HDCP_DDC_ADDR 0x3A
/* HDCP register offsets for HDMI/DVI devices */
#define DRM_HDCP_DDC_BKSV 0x00
#define DRM_HDCP_DDC_RI_PRIME 0x08
#define DRM_HDCP_DDC_AKSV 0x10
#define DRM_HDCP_DDC_AN 0x18
#define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
#define DRM_HDCP_DDC_BCAPS 0x40
#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
#define DRM_HDCP_DDC_BSTATUS 0x41
#define DRM_HDCP_DDC_KSV_FIFO 0x43
#define DRM_HDCP_1_4_SRM_ID 0x8
#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
/* Protocol message definition for HDCP2.2 specification */
/*
* Protected content streams are classified into 2 types:
* - Type0: Can be transmitted with HDCP 1.4+
* - Type1: Can be transmitted with HDCP 2.2+
*/
#define HDCP_STREAM_TYPE0 0x00
#define HDCP_STREAM_TYPE1 0x01
/* HDCP2.2 Msg IDs */
#define HDCP_2_2_NULL_MSG 1
#define HDCP_2_2_AKE_INIT 2
#define HDCP_2_2_AKE_SEND_CERT 3
#define HDCP_2_2_AKE_NO_STORED_KM 4
#define HDCP_2_2_AKE_STORED_KM 5
#define HDCP_2_2_AKE_SEND_HPRIME 7
#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8
#define HDCP_2_2_LC_INIT 9
#define HDCP_2_2_LC_SEND_LPRIME 10
#define HDCP_2_2_SKE_SEND_EKS 11
#define HDCP_2_2_REP_SEND_RECVID_LIST 12
#define HDCP_2_2_REP_SEND_ACK 15
#define HDCP_2_2_REP_STREAM_MANAGE 16
#define HDCP_2_2_REP_STREAM_READY 17
#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
#define HDCP_2_2_RTX_LEN 8
#define HDCP_2_2_RRX_LEN 8
#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128
#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3
#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
HDCP_2_2_K_PUB_RX_EXP_E_LEN)
#define HDCP_2_2_DCP_LLC_SIG_LEN 384
#define HDCP_2_2_E_KPUB_KM_LEN 128
#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16)
#define HDCP_2_2_H_PRIME_LEN 32
#define HDCP_2_2_E_KH_KM_LEN 16
#define HDCP_2_2_RN_LEN 8
#define HDCP_2_2_L_PRIME_LEN 32
#define HDCP_2_2_E_DKEY_KS_LEN 16
#define HDCP_2_2_RIV_LEN 8
#define HDCP_2_2_SEQ_NUM_LEN 3
#define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2)
#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN
#define HDCP_2_2_MAX_DEVICE_COUNT 31
#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \
HDCP_2_2_MAX_DEVICE_COUNT)
#define HDCP_2_2_MPRIME_LEN 32
/* Following Macros take a byte at a time for bit(s) masking */
/*
* TODO: This has to be changed for DP MST, as multiple stream on
* same port is possible.
* For HDCP2.2 on HDMI and DP SST this value is always 1.
*/
#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
#define HDCP_2_2_TXCAP_MASK_LEN 2
#define HDCP_2_2_RXCAPS_LEN 3
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1))
#define HDCP_2_2_RXINFO_LEN 2
/* HDCP1.x compliant device in downstream */
#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0))
/* HDCP2.0 Compliant repeater in downstream */
#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1))
#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4)
#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1)
struct hdcp2_cert_rx {
u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
u8 reserved[2];
u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
} __packed;
struct hdcp2_streamid_type {
u8 stream_id;
u8 stream_type;
} __packed;
/*
* The TxCaps field specified in the HDCP HDMI, DP specs
* This field is big endian as specified in the errata.
*/
struct hdcp2_tx_caps {
/* Transmitter must set this to 0x2 */
u8 version;
/* Reserved for HDCP and DP Spec. Read as Zero */
u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
} __packed;
/* Main structures for HDCP2.2 protocol communication */
struct hdcp2_ake_init {
u8 msg_id;
u8 r_tx[HDCP_2_2_RTX_LEN];
struct hdcp2_tx_caps tx_caps;
} __packed;
struct hdcp2_ake_send_cert {
u8 msg_id;
struct hdcp2_cert_rx cert_rx;
u8 r_rx[HDCP_2_2_RRX_LEN];
u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
} __packed;
struct hdcp2_ake_no_stored_km {
u8 msg_id;
u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
} __packed;
struct hdcp2_ake_stored_km {
u8 msg_id;
u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
} __packed;
struct hdcp2_ake_send_hprime {
u8 msg_id;
u8 h_prime[HDCP_2_2_H_PRIME_LEN];
} __packed;
struct hdcp2_ake_send_pairing_info {
u8 msg_id;
u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];
} __packed;
struct hdcp2_lc_init {
u8 msg_id;
u8 r_n[HDCP_2_2_RN_LEN];
} __packed;
struct hdcp2_lc_send_lprime {
u8 msg_id;
u8 l_prime[HDCP_2_2_L_PRIME_LEN];
} __packed;
struct hdcp2_ske_send_eks {
u8 msg_id;
u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
u8 riv[HDCP_2_2_RIV_LEN];
} __packed;
struct hdcp2_rep_send_receiverid_list {
u8 msg_id;
u8 rx_info[HDCP_2_2_RXINFO_LEN];
u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
} __packed;
struct hdcp2_rep_send_ack {
u8 msg_id;
u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
} __packed;
struct hdcp2_rep_stream_manage {
u8 msg_id;
u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
__be16 k;
struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT];
} __packed;
struct hdcp2_rep_stream_ready {
u8 msg_id;
u8 m_prime[HDCP_2_2_MPRIME_LEN];
} __packed;
struct hdcp2_dp_errata_stream_type {
u8 msg_id;
u8 stream_type;
} __packed;
/* HDCP2.2 TIMEOUTs in mSec */
#define HDCP_2_2_CERT_TIMEOUT_MS 100
#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000
#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200
#define HDCP_2_2_PAIRING_TIMEOUT_MS 200
#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20
#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7
#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000
#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100
/* HDMI HDCP2.2 Register Offsets */
#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60
#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70
#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80
#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0
#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02
#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF
#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
/* Below macros take a byte at a time and mask the bit(s) */
#define HDCP_2_2_HDMI_RXSTATUS_LEN 2
#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
/*
* Helper functions to convert 24bit big endian hdcp sequence number to
* host format and back
*/
static inline
u32 drm_hdcp2_seq_num_to_u32(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])
{
return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16);
}
static inline
void drm_hdcp2_u32_to_seq_num(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)
{
seq_num[0] = val >> 16;
seq_num[1] = val >> 8;
seq_num[2] = val;
}
#endif