zongbox@gmail.com bcae803a21

RISC-V: Enable IRQ during exception handling ...

Interrupt is allowed during exception handling.
There are warning messages if the kernel enables the configuration
'CONFIG_DEBUG_ATOMIC_SLEEP=y'.

BUG: sleeping function called from invalid context at kernel/locking/rwsem.c:23
in_atomic(): 0, irqs_disabled(): 1, pid: 43, name: ash
CPU: 0 PID: 43 Comm: ash Tainted:  G	 W	 4.15.0-rc8-00089-g89ffdae-dirty #17
Call Trace:
[<000000009abb1587>] walk_stackframe+0x0/0x7a
[<00000000d4f3d088>] ___might_sleep+0x102/0x11a
[<00000000b1fd792a>] down_read+0x18/0x28
[<000000000289ec01>] do_page_fault+0x86/0x2f6
[<00000000012441f6>] _do_fork+0x1b4/0x1e0
[<00000000f46c3e3b>] ret_from_syscall+0xa/0xe

Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2018-02-20 10:56:14 -08:00

..

vdso

RISC-V: Make __NR_riscv_flush_icache visible to userspace

2018-01-07 15:14:37 -08:00

.gitignore

RISC-V: Build Infrastructure

2017-09-26 15:26:49 -07:00

asm-offsets.c

RISC-V: Task implementation

2017-09-26 15:26:46 -07:00

cacheinfo.c

RISC-V: Init and Halt Code

2017-09-26 15:26:44 -07:00

cpu.c

RISC-V: Init and Halt Code

2017-09-26 15:26:44 -07:00

cpufeature.c

RISC-V: User-facing API

2017-09-26 15:26:48 -07:00

entry.S

RISC-V: Enable IRQ during exception handling

2018-02-20 10:56:14 -08:00

ftrace.c

riscv/ftrace: Add basic support

2018-01-30 19:10:54 -08:00

head.S

riscv: rename sptbr to satp

2018-01-30 19:16:12 -08:00

irq.c

RISC-V: Init and Halt Code

2017-09-26 15:26:44 -07:00

Makefile

riscv/ftrace: Add basic support

2018-01-30 19:10:54 -08:00

mcount.S

riscv/ftrace: Add basic support

2018-01-30 19:10:54 -08:00

module.c

RISC-V: User-facing API

2017-09-26 15:26:48 -07:00

process.c

Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

2018-01-31 19:18:12 -08:00

ptrace.c

RISC-V: User-facing API

2017-09-26 15:26:48 -07:00

reset.c

RISC-V: Init and Halt Code

2017-09-26 15:26:44 -07:00

riscv_ksyms.c

RISC-V: Export some expected symbols for modules

2017-11-30 10:01:10 -08:00

setup.c

riscv: add ZONE_DMA32

2018-01-30 19:14:27 -08:00

signal.c

RISC-V: User-facing API

2017-09-26 15:26:48 -07:00

smp.c

RISC-V: Fixes for clean allmodconfig build

2017-12-01 13:31:31 -08:00

smpboot.c

RISC-V: Init and Halt Code

2017-09-26 15:26:44 -07:00

stacktrace.c

RISC-V: Generic library routines and assembly

2017-09-26 15:26:45 -07:00

sys_riscv.c

RISC-V: Logical vs Bitwise typo

2017-12-11 07:51:06 -08:00

syscall_table.c

RISC-V: Make __NR_riscv_flush_icache visible to userspace

2018-01-07 15:14:37 -08:00

time.c

RISC-V: Init and Halt Code

2017-09-26 15:26:44 -07:00

traps.c

RISC-V: Init and Halt Code

2017-09-26 15:26:44 -07:00

vdso.c

riscv: remove redundant unlikely()

2018-01-30 19:12:06 -08:00

vmlinux.lds.S

RISC-V: Build Infrastructure

2017-09-26 15:26:49 -07:00