c11e99396d
As hw cycle counters in QCA4019 wraparound independantly in QCA4019
it is possible cycle counter and rx clear counter would wraparound
at the same time. Current logic assumes only one of the counters
would wraparound at anytime. Fix this by moving 'else' part to
another 'if'.
Fixes: 8e100354a98 ("ath10k: fix cycle counter wraparound handling for QCA4019")
Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
Reviewed-by: Julian Calaby <julian.calaby@gmail.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
222 lines
7.4 KiB
C
222 lines
7.4 KiB
C
/*
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* Copyright (c) 2014-2015 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/types.h>
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#include "core.h"
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#include "hw.h"
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const struct ath10k_hw_regs qca988x_regs = {
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.rtc_soc_base_address = 0x00004000,
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.rtc_wmac_base_address = 0x00005000,
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.soc_core_base_address = 0x00009000,
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.ce_wrapper_base_address = 0x00057000,
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.ce0_base_address = 0x00057400,
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.ce1_base_address = 0x00057800,
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.ce2_base_address = 0x00057c00,
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.ce3_base_address = 0x00058000,
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.ce4_base_address = 0x00058400,
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.ce5_base_address = 0x00058800,
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.ce6_base_address = 0x00058c00,
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.ce7_base_address = 0x00059000,
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.soc_reset_control_si0_rst_mask = 0x00000001,
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.soc_reset_control_ce_rst_mask = 0x00040000,
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.soc_chip_id_address = 0x000000ec,
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.scratch_3_address = 0x00000030,
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.fw_indicator_address = 0x00009030,
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.pcie_local_base_address = 0x00080000,
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.ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
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.ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
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.pcie_intr_fw_mask = 0x00000400,
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.pcie_intr_ce_mask_all = 0x0007f800,
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.pcie_intr_clr_address = 0x00000014,
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};
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const struct ath10k_hw_regs qca6174_regs = {
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.rtc_soc_base_address = 0x00000800,
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.rtc_wmac_base_address = 0x00001000,
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.soc_core_base_address = 0x0003a000,
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.ce_wrapper_base_address = 0x00034000,
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.ce0_base_address = 0x00034400,
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.ce1_base_address = 0x00034800,
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.ce2_base_address = 0x00034c00,
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.ce3_base_address = 0x00035000,
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.ce4_base_address = 0x00035400,
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.ce5_base_address = 0x00035800,
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.ce6_base_address = 0x00035c00,
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.ce7_base_address = 0x00036000,
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.soc_reset_control_si0_rst_mask = 0x00000000,
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.soc_reset_control_ce_rst_mask = 0x00000001,
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.soc_chip_id_address = 0x000000f0,
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.scratch_3_address = 0x00000028,
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.fw_indicator_address = 0x0003a028,
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.pcie_local_base_address = 0x00080000,
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.ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
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.ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
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.pcie_intr_fw_mask = 0x00000400,
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.pcie_intr_ce_mask_all = 0x0007f800,
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.pcie_intr_clr_address = 0x00000014,
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};
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const struct ath10k_hw_regs qca99x0_regs = {
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.rtc_soc_base_address = 0x00080000,
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.rtc_wmac_base_address = 0x00000000,
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.soc_core_base_address = 0x00082000,
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.ce_wrapper_base_address = 0x0004d000,
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.ce0_base_address = 0x0004a000,
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.ce1_base_address = 0x0004a400,
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.ce2_base_address = 0x0004a800,
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.ce3_base_address = 0x0004ac00,
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.ce4_base_address = 0x0004b000,
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.ce5_base_address = 0x0004b400,
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.ce6_base_address = 0x0004b800,
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.ce7_base_address = 0x0004bc00,
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/* Note: qca99x0 supports upto 12 Copy Engines. Other than address of
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* CE0 and CE1 no other copy engine is directly referred in the code.
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* It is not really neccessary to assign address for newly supported
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* CEs in this address table.
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* Copy Engine Address
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* CE8 0x0004c000
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* CE9 0x0004c400
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* CE10 0x0004c800
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* CE11 0x0004cc00
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*/
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.soc_reset_control_si0_rst_mask = 0x00000001,
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.soc_reset_control_ce_rst_mask = 0x00000100,
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.soc_chip_id_address = 0x000000ec,
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.scratch_3_address = 0x00040050,
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.fw_indicator_address = 0x00040050,
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.pcie_local_base_address = 0x00000000,
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.ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
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.ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
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.pcie_intr_fw_mask = 0x00100000,
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.pcie_intr_ce_mask_all = 0x000fff00,
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.pcie_intr_clr_address = 0x00000010,
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};
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const struct ath10k_hw_regs qca4019_regs = {
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.rtc_soc_base_address = 0x00080000,
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.soc_core_base_address = 0x00082000,
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.ce_wrapper_base_address = 0x0004d000,
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.ce0_base_address = 0x0004a000,
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.ce1_base_address = 0x0004a400,
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.ce2_base_address = 0x0004a800,
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.ce3_base_address = 0x0004ac00,
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.ce4_base_address = 0x0004b000,
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.ce5_base_address = 0x0004b400,
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.ce6_base_address = 0x0004b800,
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.ce7_base_address = 0x0004bc00,
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/* qca4019 supports upto 12 copy engines. Since base address
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* of ce8 to ce11 are not directly referred in the code,
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* no need have them in separate members in this table.
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* Copy Engine Address
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* CE8 0x0004c000
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* CE9 0x0004c400
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* CE10 0x0004c800
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* CE11 0x0004cc00
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*/
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.soc_reset_control_si0_rst_mask = 0x00000001,
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.soc_reset_control_ce_rst_mask = 0x00000100,
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.soc_chip_id_address = 0x000000ec,
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.fw_indicator_address = 0x0004f00c,
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.ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
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.ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
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.pcie_intr_fw_mask = 0x00100000,
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.pcie_intr_ce_mask_all = 0x000fff00,
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.pcie_intr_clr_address = 0x00000010,
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};
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const struct ath10k_hw_values qca988x_values = {
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.rtc_state_val_on = 3,
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.ce_count = 8,
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.msi_assign_ce_max = 7,
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.num_target_ce_config_wlan = 7,
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.ce_desc_meta_data_mask = 0xFFFC,
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.ce_desc_meta_data_lsb = 2,
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};
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const struct ath10k_hw_values qca6174_values = {
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.rtc_state_val_on = 3,
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.ce_count = 8,
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.msi_assign_ce_max = 7,
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.num_target_ce_config_wlan = 7,
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.ce_desc_meta_data_mask = 0xFFFC,
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.ce_desc_meta_data_lsb = 2,
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};
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const struct ath10k_hw_values qca99x0_values = {
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.rtc_state_val_on = 5,
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.ce_count = 12,
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.msi_assign_ce_max = 12,
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.num_target_ce_config_wlan = 10,
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.ce_desc_meta_data_mask = 0xFFF0,
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.ce_desc_meta_data_lsb = 4,
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};
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const struct ath10k_hw_values qca9888_values = {
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.rtc_state_val_on = 3,
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.ce_count = 12,
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.msi_assign_ce_max = 12,
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.num_target_ce_config_wlan = 10,
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.ce_desc_meta_data_mask = 0xFFF0,
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.ce_desc_meta_data_lsb = 4,
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};
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const struct ath10k_hw_values qca4019_values = {
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.ce_count = 12,
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.num_target_ce_config_wlan = 10,
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.ce_desc_meta_data_mask = 0xFFF0,
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.ce_desc_meta_data_lsb = 4,
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};
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void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
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{
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u32 cc_fix = 0;
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u32 rcc_fix = 0;
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enum ath10k_hw_cc_wraparound_type wraparound_type;
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survey->filled |= SURVEY_INFO_TIME |
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SURVEY_INFO_TIME_BUSY;
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wraparound_type = ar->hw_params.cc_wraparound_type;
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if (cc < cc_prev || rcc < rcc_prev) {
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switch (wraparound_type) {
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case ATH10K_HW_CC_WRAP_SHIFTED_ALL:
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if (cc < cc_prev) {
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cc_fix = 0x7fffffff;
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survey->filled &= ~SURVEY_INFO_TIME_BUSY;
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}
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break;
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case ATH10K_HW_CC_WRAP_SHIFTED_EACH:
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if (cc < cc_prev)
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cc_fix = 0x7fffffff;
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if (rcc < rcc_prev)
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rcc_fix = 0x7fffffff;
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break;
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case ATH10K_HW_CC_WRAP_DISABLED:
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break;
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}
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}
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cc -= cc_prev - cc_fix;
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rcc -= rcc_prev - rcc_fix;
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survey->time = CCNT_TO_MSEC(ar, cc);
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survey->time_busy = CCNT_TO_MSEC(ar, rcc);
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}
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