Dan Williams bd09626b39 cxl/pci: Find and map the RAS Capability Structure ... The RAS Capability Structure has some ancillary information that may be relevant with respect to AER events, link and protcol error status registers. Map the RAS Capability Registers in support of defining a 'struct pci_error_handlers' instance for the cxl_pci driver. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/166974412803.1608150.7096566580400947001.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2022-12-03 13:40:17 -08:00
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core	cxl/pci: Find and map the RAS Capability Structure	2022-12-03 13:40:17 -08:00
acpi.c	cxl/acpi: Minimize granularity for x1 interleaves	2022-08-01 15:36:33 -07:00
cxl.h	cxl/pci: Find and map the RAS Capability Structure	2022-12-03 13:40:17 -08:00
cxlmem.h	cxl/region: Attach endpoint decoders	2022-07-25 12:18:07 -07:00
cxlpci.h	cxl/core/regs: Make cxl_map_{component, device}_regs() device generic	2022-12-03 13:40:16 -08:00
Kconfig	cxl/region: Allocate HPA capacity to regions	2022-07-25 12:18:06 -07:00
Makefile	PM: CXL: Disable suspend	2022-04-22 16:09:42 -07:00
mem.c	cxl/mem: Enumerate port targets before adding endpoints	2022-07-21 17:19:25 -07:00
pci.c	cxl/pci: Find and map the RAS Capability Structure	2022-12-03 13:40:17 -08:00
pmem.c	cxl/pmem: Fix cxl_pmem_region and cxl_memdev leak	2022-11-04 15:58:35 -07:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00