d34f0c8ee2
Starting with Qualcomm SM8350 SoC, so Low Power Audio SubSystem (LPASS) block version v9.2, the register responsible for TX SMIC MUXn muxes is different. In earlier LPASS versions this mux had bit fields for analogue (ADCn) and digital (SWR_DMICn) MICs. Choice of ADCn was selecting the analogue path in CDC_TX_TOP_CSR_SWR_DMICn_CTL register. With LPASS v9.2 and newer, the bit fields are integrated into just SWR_MICn and there is no distinction for analogue or digital MIC in the register. Fix support for LPASS v9.2+: 1. Add new set of widgets and audio routes for LPASS v9.2. 2. Do not choose analogue or digital in CDC_TX_TOP_CSR_SWR_DMICn_CTL based on value of the mux. 3. Replace all the input widgets (TX SWR_ADCn, TX SWR_DMICn) with TX SWR_INPUTn ones. The change is not backwards compatible with older DTBs and existing mixer settings, therefore it does not change handling of older platforms with working micrphones (SC8280xp) but only the ones with issues (SM8450, SM8550) which need the fix. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://msgid.link/r/20240226115925.53953-3-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
30 lines
696 B
C
30 lines
696 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
|
|
*/
|
|
|
|
#ifndef __LPASS_MACRO_COMMON_H__
|
|
#define __LPASS_MACRO_COMMON_H__
|
|
|
|
/* NPL clock is expected */
|
|
#define LPASS_MACRO_FLAG_HAS_NPL_CLOCK BIT(0)
|
|
/* The soundwire block should be internally reset at probe */
|
|
#define LPASS_MACRO_FLAG_RESET_SWR BIT(1)
|
|
|
|
enum lpass_version {
|
|
LPASS_VER_9_0_0,
|
|
LPASS_VER_9_2_0,
|
|
LPASS_VER_10_0_0,
|
|
LPASS_VER_11_0_0,
|
|
};
|
|
|
|
struct lpass_macro {
|
|
struct device *macro_pd;
|
|
struct device *dcodec_pd;
|
|
};
|
|
|
|
struct lpass_macro *lpass_macro_pds_init(struct device *dev);
|
|
void lpass_macro_pds_exit(struct lpass_macro *pds);
|
|
|
|
#endif /* __LPASS_MACRO_COMMON_H__ */
|