bdc42353ba
The Exynos4412 has the same watchdog as newer SoCs (e.g. Exynos5250). Just like the others, for working it requires additional steps in Power Management Unit: unmasking the reset request and enabling the system reset. Without these additional steps in PMU, the watchdog will not be able to reset the system on expiration event. Change the compatible of Exynos4412 watchdog device node to samsung,exynos5250-wdt which includes the additional PMU steps. This will also fix infinite watchdog interrupt in soft mode (lack of interrupt clear) because it is also included in samsung,exynos5250-wdt. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Guenter Roeck <linux@roeck-us.net>
475 lines
11 KiB
Plaintext
475 lines
11 KiB
Plaintext
/*
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* Samsung's Exynos4210 SoC device tree source
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2010-2011 Linaro Ltd.
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* www.linaro.org
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*
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* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
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* based board files can include this file and provide values for board specfic
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos4.dtsi"
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#include "exynos4210-pinctrl.dtsi"
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#include "exynos4-cpu-thermal.dtsi"
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/ {
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compatible = "samsung,exynos4210", "samsung,exynos4";
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@900 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x900>;
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clocks = <&clock CLK_ARM_CLK>;
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clock-names = "cpu";
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clock-latency = <160000>;
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operating-points = <
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1200000 1250000
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1000000 1150000
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800000 1075000
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500000 975000
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400000 975000
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200000 950000
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>;
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cooling-min-level = <4>;
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cooling-max-level = <2>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu@901 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x901>;
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};
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};
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sysram: sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x20000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@1f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x1f000 0x1000>;
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};
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};
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pd_lcd1: lcd1-power-domain@10023CA0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CA0 0x20>;
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#power-domain-cells = <0>;
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label = "LCD1";
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};
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l2c: l2-cache-controller@10502000 {
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compatible = "arm,pl310-cache";
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reg = <0x10502000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,tag-latency = <2 2 1>;
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arm,data-latency = <2 2 1>;
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};
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mct: mct@10050000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10050000 0x800>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
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<1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
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<2 &combiner 12 6>,
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<3 &combiner 12 7>,
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<4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
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<5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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watchdog: watchdog@10060000 {
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compatible = "samsung,s3c2410-wdt";
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reg = <0x10060000 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_WDT>;
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clock-names = "watchdog";
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status = "disabled";
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};
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4210-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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wakup_eint: wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl_2: pinctrl@03860000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x03860000 0x1000>;
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};
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tmu: tmu@100C0000 {
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compatible = "samsung,exynos4210-tmu";
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interrupt-parent = <&combiner>;
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reg = <0x100C0000 0x100>;
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interrupts = <2 4>;
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clocks = <&clock CLK_TMU_APBIF>;
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clock-names = "tmu_apbif";
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samsung,tmu_gain = <15>;
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samsung,tmu_reference_voltage = <7>;
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status = "disabled";
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tmu 0>;
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trips {
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cpu_alert0: cpu-alert-0 {
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temperature = <85000>; /* millicelsius */
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};
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cpu_alert1: cpu-alert-1 {
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temperature = <100000>; /* millicelsius */
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};
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cpu_alert2: cpu-alert-2 {
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temperature = <110000>; /* millicelsius */
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};
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};
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};
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};
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g2d: g2d@12800000 {
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compatible = "samsung,s5pv210-g2d";
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reg = <0x12800000 0x1000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
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clock-names = "sclk_fimg2d", "fimg2d";
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power-domains = <&pd_lcd0>;
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iommus = <&sysmmu_g2d>;
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};
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camera {
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clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
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<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
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clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
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fimc_0: fimc@11800000 {
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,cam-if;
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};
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fimc_1: fimc@11810000 {
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,cam-if;
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};
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fimc_2: fimc@11820000 {
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,lcd-wb;
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};
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fimc_3: fimc@11830000 {
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samsung,pix-limits = <1920 8192 1366 1920>;
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samsung,rotators = <0>;
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samsung,mainscaler-ext;
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samsung,lcd-wb;
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};
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};
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mixer: mixer@12C10000 {
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clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
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"sclk_mixer";
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clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
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<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
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<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
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};
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ppmu_lcd1: ppmu_lcd1@12240000 {
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compatible = "samsung,exynos-ppmu";
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reg = <0x12240000 0x2000>;
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clocks = <&clock CLK_PPMULCD1>;
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clock-names = "ppmu";
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status = "disabled";
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};
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sysmmu_g2d: sysmmu@12A20000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x12A20000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <4 7>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
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power-domains = <&pd_lcd0>;
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#iommu-cells = <0>;
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};
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sysmmu_fimd1: sysmmu@12220000 {
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compatible = "samsung,exynos-sysmmu";
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interrupt-parent = <&combiner>;
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reg = <0x12220000 0x1000>;
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interrupts = <5 3>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
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power-domains = <&pd_lcd1>;
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#iommu-cells = <0>;
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};
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bus_dmc: bus_dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_acp: bus_acp {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_ACP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_acp_opp_table>;
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status = "disabled";
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};
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bus_peri: bus_peri {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK100>;
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clock-names = "bus";
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operating-points-v2 = <&bus_peri_opp_table>;
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status = "disabled";
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};
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bus_fsys: bus_fsys {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK133>;
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clock-names = "bus";
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operating-points-v2 = <&bus_fsys_opp_table>;
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status = "disabled";
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};
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bus_display: bus_display {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK160>;
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clock-names = "bus";
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operating-points-v2 = <&bus_display_opp_table>;
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status = "disabled";
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};
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bus_lcd0: bus_lcd0 {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK200>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_leftbus: bus_leftbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDL>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_rightbus: bus_rightbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDR>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_mfc: bus_mfc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_SCLK_MFC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_dmc_opp_table: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <1025000>;
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};
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opp@267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <1050000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1150000>;
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};
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};
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bus_acp_opp_table: opp_table2 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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};
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bus_peri_opp_table: opp_table3 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@5000000 {
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opp-hz = /bits/ 64 <5000000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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};
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bus_fsys_opp_table: opp_table4 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@10000000 {
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opp-hz = /bits/ 64 <10000000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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};
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bus_display_opp_table: opp_table5 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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};
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bus_leftbus_opp_table: opp_table6 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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};
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};
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&gic {
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cpu-offset = <0x8000>;
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};
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&combiner {
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samsung,combiner-nr = <16>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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&mdma1 {
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power-domains = <&pd_lcd0>;
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};
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&pmu_system_controller {
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clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
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"clkout4", "clkout8", "clkout9";
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clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
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<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
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<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
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#clock-cells = <1>;
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};
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&rotator {
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power-domains = <&pd_lcd0>;
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};
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&sysmmu_rotator {
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power-domains = <&pd_lcd0>;
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};
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