be227f8e99
Now that DMA ops are part of the core API via iommu-dma, fold the vestigial remains of the IOMMU_DMA_OPS init state into the IOMMU API phase, and clean up a few other leftovers. This should also close the race window wherein bus_set_iommu() effectively makes the DMA ops state visible before its nominal initialisation - it seems this was previously fairly benign, but since commita250c23f15("iommu: remove DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE") it can now lead to the strict flush queue policy inadvertently being picked for default domains allocated during that window, with a corresponding unexpected perfomance impact. Reported-by: Jussi Maki <joamaki@gmail.com> Tested-by: Jussi Maki <joamaki@gmail.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Fixes:a250c23f15("iommu: remove DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE") Link: https://lore.kernel.org/r/665db61e23ff8d54ac5eb391bef520b3a803fcb9.1622727974.git.robin.murphy@arm.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
133 lines
4.2 KiB
C
133 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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#ifndef AMD_IOMMU_H
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#define AMD_IOMMU_H
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#include <linux/iommu.h>
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#include "amd_iommu_types.h"
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extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
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extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
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extern void amd_iommu_apply_erratum_63(u16 devid);
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extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
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extern int amd_iommu_init_devices(void);
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extern void amd_iommu_uninit_devices(void);
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extern void amd_iommu_init_notifier(void);
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extern int amd_iommu_init_api(void);
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#ifdef CONFIG_AMD_IOMMU_DEBUGFS
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void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
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#else
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static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
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#endif
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/* Needed for interrupt remapping */
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extern int amd_iommu_prepare(void);
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extern int amd_iommu_enable(void);
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extern void amd_iommu_disable(void);
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extern int amd_iommu_reenable(int);
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extern int amd_iommu_enable_faulting(void);
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extern int amd_iommu_guest_ir;
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extern enum io_pgtable_fmt amd_iommu_pgtable;
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/* IOMMUv2 specific functions */
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struct iommu_domain;
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extern bool amd_iommu_v2_supported(void);
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extern struct amd_iommu *get_amd_iommu(unsigned int idx);
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extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
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extern bool amd_iommu_pc_supported(void);
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extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
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extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value);
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extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value);
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extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
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extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
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extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
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extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
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extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
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u64 address);
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extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
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extern void amd_iommu_domain_update(struct protection_domain *domain);
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extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
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extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
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extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
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extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
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unsigned long cr3);
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extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
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#ifdef CONFIG_IRQ_REMAP
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extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
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#else
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static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
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{
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return 0;
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}
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#endif
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#define PPR_SUCCESS 0x0
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#define PPR_INVALID 0x1
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#define PPR_FAILURE 0xf
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extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
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int status, int tag);
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static inline bool is_rd890_iommu(struct pci_dev *pdev)
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{
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return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
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(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
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}
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static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
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{
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return !!(iommu->features & mask);
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}
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static inline u64 iommu_virt_to_phys(void *vaddr)
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{
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return (u64)__sme_set(virt_to_phys(vaddr));
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}
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static inline void *iommu_phys_to_virt(unsigned long paddr)
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{
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return phys_to_virt(__sme_clr(paddr));
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}
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static inline
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void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
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{
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atomic64_set(&domain->iop.pt_root, root);
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domain->iop.root = (u64 *)(root & PAGE_MASK);
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domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
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}
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static inline
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void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
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{
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amd_iommu_domain_set_pt_root(domain, 0);
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}
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extern bool translation_pre_enabled(struct amd_iommu *iommu);
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extern bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
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struct device *dev);
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extern int __init add_special_device(u8 type, u8 id, u16 *devid,
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bool cmd_line);
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#ifdef CONFIG_DMI
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void amd_iommu_apply_ivrs_quirks(void);
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#else
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static inline void amd_iommu_apply_ivrs_quirks(void) { }
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#endif
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extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
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u64 *root, int mode);
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#endif
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