Peter De Schrijver bf161d2163 clk: tegra: No 7.1 super clk dividers on Tegra20 ... Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. Remove the clocks related to the divider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>		2013-03-11 14:29:22 -06:00
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clk-audio-sync.c
clk-divider.c
clk-periph-gate.c
clk-periph.c	ARM: tegra: migrate to new clock code	2013-01-28 11:19:07 -07:00
clk-pll-out.c
clk-pll.c
clk-super.c	clk: tegra: Implement locking for super clock	2013-02-12 10:29:12 -07:00
clk-tegra20.c	clk: tegra: No 7.1 super clk dividers on Tegra20	2013-03-11 14:29:22 -06:00
clk-tegra30.c	clk: tegra: initialise parent of uart clocks	2013-02-13 11:17:03 -07:00
clk.c	ARM: tegra: migrate to new clock code	2013-01-28 11:19:07 -07:00
clk.h	clk: tegra: add clock support for Tegra30	2013-01-28 11:19:07 -07:00
Makefile	clk: tegra: add clock support for Tegra30	2013-01-28 11:19:07 -07:00