Lee Jones 1609634d41 clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc' ...

Fixes the following W=1 kernel build warning(s):

 drivers/clk/socfpga/clk-pll-a10.c: In function ‘__socfpga_pll_init’:
 drivers/clk/socfpga/clk-pll-a10.c:76:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable]

Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-9-lee.jones@linaro.org
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

2021-02-11 11:56:06 -08:00

..

clk-agilex.c

clk: socfpga: agilex: Remove unused variable 'cntr_mux'

2020-09-22 12:46:12 -07:00

clk-gate-a10.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30 11:29:52 -07:00

clk-gate-s10.c

clk: socfpga: stratix10: use new parent data scheme

2020-05-26 19:13:05 -07:00

clk-gate.c

clk: socfpga: deindent code to proper indentation

2019-08-16 10:20:07 -07:00

clk-periph-a10.c

clk: socfpga: Don't reference clk_init_data after registration

2019-08-16 10:20:07 -07:00

clk-periph-s10.c

clk: socfpga: stratix10: use new parent data scheme

2020-05-26 19:13:05 -07:00

clk-periph.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-pll-a10.c

clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'

2021-02-11 11:56:06 -08:00

clk-pll-s10.c

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00

clk-pll.c

clk: socfpga: clk-pll: Remove unused variable 'rc'

2021-02-11 11:56:06 -08:00

clk-s10.c

clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk

2020-09-22 12:54:41 -07:00

clk.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13

2019-05-21 11:28:45 +02:00

clk.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

2019-06-05 17:36:37 +02:00

Makefile

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00

stratix10-clk.h

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00