ShihPo Hung bf587caae3 riscv: mm: synchronize MMU after pte change ... Because RISC-V compliant implementations can cache invalid entries in TLB, an SFENCE.VMA is necessary after changes to the page table. This patch adds an SFENCE.vma for the vmalloc_fault path. Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com> [paul.walmsley@sifive.com: reversed tab->whitespace conversion, wrapped comment lines] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: linux-riscv@lists.infradead.org Cc: stable@vger.kernel.org		2019-06-17 03:44:44 -07:00
..
cacheflush.c	riscv: move flush_icache_{all,mm} to cacheflush.c	2019-05-16 20:42:12 -07:00
context.c	riscv: move switch_mm to its own file	2019-05-16 20:42:12 -07:00
extable.c
fault.c	riscv: mm: synchronize MMU after pte change	2019-06-17 03:44:44 -07:00
init.c	riscv: switch over to generic free_initmem()	2019-05-14 09:47:47 -07:00
ioremap.c	RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap	2018-10-22 17:02:56 -07:00
Makefile	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	2019-05-16 20:42:13 -07:00
sifive_l2_cache.c	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	2019-05-16 20:42:13 -07:00