bf6f146f32
These are only available on the Meson8m2 SoC (which uses the same DesignWare Ethernet MAC as Meson8b). The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII PHYs or the RGMII TX clock (as far as we know the frequency is controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP block). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| pinctrl-meson8-pmx.c | ||
| pinctrl-meson8-pmx.h | ||
| pinctrl-meson8.c | ||
| pinctrl-meson8b.c | ||
| pinctrl-meson-axg-pmx.c | ||
| pinctrl-meson-axg-pmx.h | ||
| pinctrl-meson-axg.c | ||
| pinctrl-meson-gxbb.c | ||
| pinctrl-meson-gxl.c | ||
| pinctrl-meson.c | ||
| pinctrl-meson.h | ||