33cd7c6fff
The Devicetree bindings document does not have to say in the title that
it is a "Devicetree binding", but instead just describe the hardware.
Drop "Devicetree bindings" in various forms:
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-exec sed -i -e 's/^title: [dD]evice[ -]\?[tT]ree [cC]lock [bB]indings\? for \([tT]he \)\?\(.*\)$/title: \u\2 Clock Controller/' {} \;
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-exec sed -i -e 's/^title: [cC]lock [bB]indings\? for \([tT]he \)\?\(.*\)$/title: \u\2 Clock Controller/' {} \;
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Link: https://lore.kernel.org/r/20221216163815.522628-9-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
89 lines
2.6 KiB
YAML
89 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
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maintainers:
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- A.s. Dong <aisheng.dong@nxp.com>
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description: |
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i.MX7ULP Clock functions are under joint control of the System
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Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
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modules, and Core Mode Controller (CMC)1 blocks
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The clocking scheme provides clear separation between M4 domain
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and A7 domain. Except for a few clock sources shared between two
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domains, such as the System Oscillator clock, the Slow IRC (SIRC),
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and and the Fast IRC clock (FIRCLK), clock sources and clock
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management are separated and contained within each domain.
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M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
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A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
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Note: this binding doc is only for A7 clock domain.
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The System Clock Generation (SCG) is responsible for clock generation
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and distribution across this device. Functions performed by the SCG
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include: clock reference selection, generation of clock used to derive
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processor, system, peripheral bus and external memory interface clocks,
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source selection for peripheral clocks and control of power saving
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clock gating mode.
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
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i.MX7ULP clock IDs of each module.
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properties:
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compatible:
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const: fsl,imx7ulp-scg1
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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items:
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- description: rtc osc
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- description: system osc
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- description: slow internal reference clock
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- description: fast internal reference clock
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- description: usb PLL
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clock-names:
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items:
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- const: rosc
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- const: sosc
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- const: sirc
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- const: firc
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- const: upll
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx7ulp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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clock-controller@403e0000 {
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compatible = "fsl,imx7ulp-scg1";
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reg = <0x403e0000 0x10000>;
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clocks = <&rosc>, <&sosc>, <&sirc>,
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<&firc>, <&upll>;
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clock-names = "rosc", "sosc", "sirc",
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"firc", "upll";
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#clock-cells = <1>;
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};
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