7fce1e39f0
Add bindings for the system clock and reset generator (SYSCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
105 lines
3.0 KiB
YAML
105 lines
3.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System Clock and Reset Generator
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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properties:
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compatible:
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const: starfive,jh7110-syscrg
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC1 RMII reference or GMAC1 RGMII RX
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- description: External I2S TX bit clock
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- description: External I2S TX left/right channel clock
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- description: External I2S RX bit clock
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC1 RMII reference
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- description: GMAC1 RGMII RX
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- description: External I2S TX bit clock
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- description: External I2S TX left/right channel clock
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- description: External I2S RX bit clock
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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clock-names:
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oneOf:
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- items:
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- const: osc
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- enum:
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- gmac1_rmii_refin
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- gmac1_rgmii_rxin
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- const: i2stx_bclk_ext
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- const: i2stx_lrck_ext
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- const: i2srx_bclk_ext
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- items:
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- const: osc
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- const: gmac1_rmii_refin
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- const: gmac1_rgmii_rxin
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- const: i2stx_bclk_ext
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- const: i2stx_lrck_ext
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- const: i2srx_bclk_ext
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@13020000 {
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compatible = "starfive,jh7110-syscrg";
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reg = <0x13020000 0x10000>;
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clocks = <&osc>, <&gmac1_rmii_refin>,
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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<&tdm_ext>, <&mclk_ext>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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"tdm_ext", "mclk_ext";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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