c218bca74e
With system caches for the host OS or architected caches for guest OS we cannot easily guarantee that there are no dirty or stale cache lines for the areas of memory written by the kernel during boot with the MMU off (therefore non-cacheable accesses). This patch adds the necessary cache maintenance during boot and relaxes the booting requirements. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
186 lines
7.1 KiB
Plaintext
186 lines
7.1 KiB
Plaintext
Booting AArch64 Linux
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=====================
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Author: Will Deacon <will.deacon@arm.com>
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Date : 07 September 2012
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This document is based on the ARM booting document by Russell King and
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is relevant to all public releases of the AArch64 Linux kernel.
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The AArch64 exception model is made up of a number of exception levels
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(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
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counterpart. EL2 is the hypervisor level and exists only in non-secure
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mode. EL3 is the highest priority level and exists only in secure mode.
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For the purposes of this document, we will use the term `boot loader'
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simply to define all software that executes on the CPU(s) before control
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is passed to the Linux kernel. This may include secure monitor and
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hypervisor code, or it may just be a handful of instructions for
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preparing a minimal boot environment.
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Essentially, the boot loader should provide (as a minimum) the
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following:
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1. Setup and initialise the RAM
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2. Setup the device tree
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3. Decompress the kernel image
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4. Call the kernel image
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1. Setup and initialise RAM
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---------------------------
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Requirement: MANDATORY
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The boot loader is expected to find and initialise all RAM that the
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kernel will use for volatile data storage in the system. It performs
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this in a machine dependent manner. (It may use internal algorithms
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to automatically locate and size all RAM, or it may use knowledge of
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the RAM in the machine, or any other method the boot loader designer
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sees fit.)
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2. Setup the device tree
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-------------------------
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Requirement: MANDATORY
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The device tree blob (dtb) must be placed on an 8-byte boundary within
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the first 512 megabytes from the start of the kernel image and must not
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cross a 2-megabyte boundary. This is to allow the kernel to map the
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blob using a single section mapping in the initial page tables.
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3. Decompress the kernel image
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------------------------------
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Requirement: OPTIONAL
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The AArch64 kernel does not currently provide a decompressor and
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therefore requires decompression (gzip etc.) to be performed by the boot
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loader if a compressed Image target (e.g. Image.gz) is used. For
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bootloaders that do not implement this requirement, the uncompressed
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Image target is available instead.
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4. Call the kernel image
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------------------------
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Requirement: MANDATORY
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The decompressed kernel image contains a 64-byte header as follows:
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u32 code0; /* Executable code */
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u32 code1; /* Executable code */
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u64 text_offset; /* Image load offset */
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u64 res0 = 0; /* reserved */
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u64 res1 = 0; /* reserved */
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u64 res2 = 0; /* reserved */
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u64 res3 = 0; /* reserved */
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u64 res4 = 0; /* reserved */
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u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */
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u32 res5 = 0; /* reserved */
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Header notes:
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- code0/code1 are responsible for branching to stext.
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The image must be placed at the specified offset (currently 0x80000)
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from the start of the system RAM and called there. The start of the
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system RAM must be aligned to 2MB.
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Before jumping into the kernel, the following conditions must be met:
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- Quiesce all DMA capable devices so that memory does not get
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corrupted by bogus network packets or disk data. This will save
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you many hours of debug.
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- Primary CPU general-purpose register settings
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x0 = physical address of device tree blob (dtb) in system RAM.
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x1 = 0 (reserved for future use)
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x2 = 0 (reserved for future use)
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x3 = 0 (reserved for future use)
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- CPU mode
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All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
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IRQ and FIQ).
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The CPU must be in either EL2 (RECOMMENDED in order to have access to
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the virtualisation extensions) or non-secure EL1.
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- Caches, MMUs
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The MMU must be off.
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Instruction cache may be on or off.
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The address range corresponding to the loaded kernel image must be
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cleaned to the PoC. In the presence of a system cache or other
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coherent masters with caches enabled, this will typically require
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cache maintenance by VA rather than set/way operations.
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System caches which respect the architected cache maintenance by VA
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operations must be configured and may be enabled.
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System caches which do not respect architected cache maintenance by VA
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operations (not recommended) must be configured and disabled.
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- Architected timers
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CNTFRQ must be programmed with the timer frequency and CNTVOFF must
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be programmed with a consistent value on all CPUs. If entering the
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kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
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available.
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- Coherency
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All CPUs to be booted by the kernel must be part of the same coherency
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domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
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initialisation to enable the receiving of maintenance operations on
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each CPU.
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- System registers
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All writable architected system registers at the exception level where
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the kernel image will be entered must be initialised by software at a
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higher exception level to prevent execution in an UNKNOWN state.
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The requirements described above for CPU mode, caches, MMUs, architected
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timers, coherency and system registers apply to all CPUs. All CPUs must
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enter the kernel in the same exception level.
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The boot loader is expected to enter the kernel on each CPU in the
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following manner:
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- The primary CPU must jump directly to the first instruction of the
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kernel image. The device tree blob passed by this CPU must contain
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an 'enable-method' property for each cpu node. The supported
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enable-methods are described below.
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It is expected that the bootloader will generate these device tree
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properties and insert them into the blob prior to kernel entry.
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- CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
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property in their cpu node. This property identifies a
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naturally-aligned 64-bit zero-initalised memory location.
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These CPUs should spin outside of the kernel in a reserved area of
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memory (communicated to the kernel by a /memreserve/ region in the
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device tree) polling their cpu-release-addr location, which must be
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contained in the reserved region. A wfe instruction may be inserted
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to reduce the overhead of the busy-loop and a sev will be issued by
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the primary CPU. When a read of the location pointed to by the
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cpu-release-addr returns a non-zero value, the CPU must jump to this
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value. The value will be written as a single 64-bit little-endian
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value, so CPUs must convert the read value to their native endianness
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before jumping to it.
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- CPUs with a "psci" enable method should remain outside of
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the kernel (i.e. outside of the regions of memory described to the
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kernel in the memory node, or in a reserved area of memory described
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to the kernel by a /memreserve/ region in the device tree). The
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kernel will issue CPU_ON calls as described in ARM document number ARM
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DEN 0022A ("Power State Coordination Interface System Software on ARM
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processors") to bring CPUs into the kernel.
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The device tree should contain a 'psci' node, as described in
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Documentation/devicetree/bindings/arm/psci.txt.
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- Secondary CPU general-purpose register settings
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x0 = 0 (reserved for future use)
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x1 = 0 (reserved for future use)
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x2 = 0 (reserved for future use)
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x3 = 0 (reserved for future use)
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