c26d0d87f1
Add support for Cypress s25fs128s1 flash. Previously the flash is decoded as s25fl129p1 by mistake. Add it in the flash info list to correctly decode. The flash also needs a fixup for s25fs-s family. Further capability of the flash will be parsed from bfpt. The flash has been tested under SPI/DUAL/QUAD mode on hisi-sfc-v3xx controller, all the write/read/erase works well. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
122 lines
4.6 KiB
C
122 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static int
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s25fs_s_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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/*
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* The S25FS-S chip family reports 512-byte pages in BFPT but
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* in reality the write buffer still wraps at the safe default
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* of 256 bytes. Overwrite the page size advertised by BFPT
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* to get the writes working.
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*/
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params->page_size = 256;
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return 0;
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}
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static struct spi_nor_fixups s25fs_s_fixups = {
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.post_bfpt = s25fs_s_post_bfpt_fixups,
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};
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static const struct flash_info spansion_parts[] = {
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/* Spansion/Cypress -- single (large) sector size only, at least
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* for the chips listed here (without boot sectors).
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*/
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | USE_CLSR) },
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{ "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
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.fixups = &s25fs_s_fixups, },
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{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
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.fixups = &s25fs_s_fixups, },
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{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
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{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
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{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
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{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
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{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
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{ "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
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{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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};
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static void spansion_post_sfdp_fixups(struct spi_nor *nor)
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{
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if (nor->params->size <= SZ_16M)
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return;
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nor->flags |= SNOR_F_4B_OPCODES;
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/* No small sector erase for 4-byte command set */
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nor->erase_opcode = SPINOR_OP_SE;
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nor->mtd.erasesize = nor->info->sector_size;
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}
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static const struct spi_nor_fixups spansion_fixups = {
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.post_sfdp = spansion_post_sfdp_fixups,
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};
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const struct spi_nor_manufacturer spi_nor_spansion = {
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.name = "spansion",
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.parts = spansion_parts,
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.nparts = ARRAY_SIZE(spansion_parts),
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.fixups = &spansion_fixups,
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};
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