4e31b808fa
Now that we actually read registers from QSGMII PCSs, it's important that we have the correct address (instead of hoping that we're the MAC with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII PCSs. They have the same addresses on all SoCs (e.g. if QSGMIIA is present it's used for MACs 1 through 4). Since the first QSGMII PCSs share an address with the SGMII and XFI PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts on the bus. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: David S. Miller <davem@davemloft.net>
46 lines
1.0 KiB
Plaintext
46 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
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/*
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* QorIQ FMan v3 10g port #3 device tree stub [ controller @ offset 0x400000 ]
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*
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* Copyright 2022 Sean Anderson <sean.anderson@seco.com>
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* Copyright 2012 - 2015 Freescale Semiconductor Inc.
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*/
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fman@400000 {
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fman0_rx_0x09: port@89000 {
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cell-index = <0x9>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x89000 0x1000>;
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fsl,fman-10g-port;
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};
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fman0_tx_0x29: port@a9000 {
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cell-index = <0x29>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xa9000 0x1000>;
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fsl,fman-10g-port;
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};
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ethernet@e2000 {
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cell-index = <1>;
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compatible = "fsl,fman-memac";
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reg = <0xe2000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
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ptp-timer = <&ptp_timer0>;
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pcsphy-handle = <&pcsphy1>, <&pcsphy1>;
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pcs-handle-names = "sgmii", "xfi";
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};
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mdio@e3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xe3000 0x1000>;
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fsl,erratum-a011043; /* must ignore read errors */
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pcsphy1: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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