c2b0acde06
No need to check whether interrupt pending for MSI(X) and conversely, no need to check whether MSI(X) interrupts are being used when checking if interrupts are pending. Reviewed-by: Scott Teel <scott.teel@pmcs.com> Signed-off-by: Don Brace <don.brace@pmcs.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
571 lines
17 KiB
C
571 lines
17 KiB
C
/*
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* Disk Array driver for HP Smart Array SAS controllers
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* Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Questions/Comments/Bugfixes to iss_storagedev@hp.com
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*
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*/
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#ifndef HPSA_H
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#define HPSA_H
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#include <scsi/scsicam.h>
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#define IO_OK 0
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#define IO_ERROR 1
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struct ctlr_info;
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struct access_method {
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void (*submit_command)(struct ctlr_info *h,
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struct CommandList *c);
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void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
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bool (*intr_pending)(struct ctlr_info *h);
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unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
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};
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struct hpsa_scsi_dev_t {
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int devtype;
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int bus, target, lun; /* as presented to the OS */
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unsigned char scsi3addr[8]; /* as presented to the HW */
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#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
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unsigned char device_id[16]; /* from inquiry pg. 0x83 */
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unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
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unsigned char model[16]; /* bytes 16-31 of inquiry data */
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unsigned char raid_level; /* from inquiry page 0xC1 */
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unsigned char volume_offline; /* discovered via TUR or VPD */
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u16 queue_depth; /* max queue_depth for this device */
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atomic_t ioaccel_cmds_out; /* Only used for physical devices
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* counts commands sent to physical
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* device via "ioaccel" path.
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*/
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u32 ioaccel_handle;
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int offload_config; /* I/O accel RAID offload configured */
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int offload_enabled; /* I/O accel RAID offload enabled */
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int offload_to_mirror; /* Send next I/O accelerator RAID
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* offload request to mirror drive
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*/
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struct raid_map_data raid_map; /* I/O accelerator RAID map */
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/*
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* Pointers from logical drive map indices to the phys drives that
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* make those logical drives. Note, multiple logical drives may
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* share physical drives. You can have for instance 5 physical
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* drives with 3 logical drives each using those same 5 physical
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* disks. We need these pointers for counting i/o's out to physical
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* devices in order to honor physical device queue depth limits.
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*/
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struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
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};
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struct reply_queue_buffer {
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u64 *head;
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size_t size;
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u8 wraparound;
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u32 current_entry;
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dma_addr_t busaddr;
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};
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#pragma pack(1)
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struct bmic_controller_parameters {
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u8 led_flags;
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u8 enable_command_list_verification;
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u8 backed_out_write_drives;
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u16 stripes_for_parity;
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u8 parity_distribution_mode_flags;
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u16 max_driver_requests;
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u16 elevator_trend_count;
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u8 disable_elevator;
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u8 force_scan_complete;
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u8 scsi_transfer_mode;
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u8 force_narrow;
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u8 rebuild_priority;
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u8 expand_priority;
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u8 host_sdb_asic_fix;
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u8 pdpi_burst_from_host_disabled;
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char software_name[64];
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char hardware_name[32];
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u8 bridge_revision;
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u8 snapshot_priority;
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u32 os_specific;
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u8 post_prompt_timeout;
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u8 automatic_drive_slamming;
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u8 reserved1;
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u8 nvram_flags;
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#define HBA_MODE_ENABLED_FLAG (1 << 3)
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u8 cache_nvram_flags;
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u8 drive_config_flags;
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u16 reserved2;
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u8 temp_warning_level;
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u8 temp_shutdown_level;
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u8 temp_condition_reset;
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u8 max_coalesce_commands;
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u32 max_coalesce_delay;
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u8 orca_password[4];
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u8 access_id[16];
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u8 reserved[356];
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};
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#pragma pack()
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struct ctlr_info {
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int ctlr;
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char devname[8];
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char *product_name;
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struct pci_dev *pdev;
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u32 board_id;
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void __iomem *vaddr;
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unsigned long paddr;
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int nr_cmds; /* Number of commands allowed on this controller */
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#define HPSA_CMDS_RESERVED_FOR_ABORTS 2
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#define HPSA_CMDS_RESERVED_FOR_DRIVER 1
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struct CfgTable __iomem *cfgtable;
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int interrupts_enabled;
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int max_commands;
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int last_allocation;
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atomic_t commands_outstanding;
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# define PERF_MODE_INT 0
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# define DOORBELL_INT 1
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# define SIMPLE_MODE_INT 2
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# define MEMQ_MODE_INT 3
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unsigned int intr[MAX_REPLY_QUEUES];
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unsigned int msix_vector;
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unsigned int msi_vector;
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int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
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struct access_method access;
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char hba_mode_enabled;
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/* queue and queue Info */
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unsigned int Qdepth;
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unsigned int maxSG;
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spinlock_t lock;
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int maxsgentries;
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u8 max_cmd_sg_entries;
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int chainsize;
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struct SGDescriptor **cmd_sg_list;
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/* pointers to command and error info pool */
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struct CommandList *cmd_pool;
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dma_addr_t cmd_pool_dhandle;
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struct io_accel1_cmd *ioaccel_cmd_pool;
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dma_addr_t ioaccel_cmd_pool_dhandle;
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struct io_accel2_cmd *ioaccel2_cmd_pool;
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dma_addr_t ioaccel2_cmd_pool_dhandle;
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struct ErrorInfo *errinfo_pool;
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dma_addr_t errinfo_pool_dhandle;
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unsigned long *cmd_pool_bits;
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int scan_finished;
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spinlock_t scan_lock;
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wait_queue_head_t scan_wait_queue;
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struct Scsi_Host *scsi_host;
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spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
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int ndevices; /* number of used elements in .dev[] array. */
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struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
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/*
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* Performant mode tables.
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*/
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u32 trans_support;
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u32 trans_offset;
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struct TransTable_struct __iomem *transtable;
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unsigned long transMethod;
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/* cap concurrent passthrus at some reasonable maximum */
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#define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
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atomic_t passthru_cmds_avail;
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/*
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* Performant mode completion buffers
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*/
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size_t reply_queue_size;
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struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
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u8 nreply_queues;
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u32 *blockFetchTable;
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u32 *ioaccel1_blockFetchTable;
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u32 *ioaccel2_blockFetchTable;
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u32 __iomem *ioaccel2_bft2_regs;
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unsigned char *hba_inquiry_data;
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u32 driver_support;
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u32 fw_support;
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int ioaccel_support;
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int ioaccel_maxsg;
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u64 last_intr_timestamp;
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u32 last_heartbeat;
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u64 last_heartbeat_timestamp;
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u32 heartbeat_sample_interval;
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atomic_t firmware_flash_in_progress;
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u32 __percpu *lockup_detected;
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struct delayed_work monitor_ctlr_work;
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int remove_in_progress;
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/* Address of h->q[x] is passed to intr handler to know which queue */
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u8 q[MAX_REPLY_QUEUES];
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u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
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#define HPSATMF_BITS_SUPPORTED (1 << 0)
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#define HPSATMF_PHYS_LUN_RESET (1 << 1)
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#define HPSATMF_PHYS_NEX_RESET (1 << 2)
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#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
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#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
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#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
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#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
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#define HPSATMF_PHYS_QRY_TASK (1 << 7)
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#define HPSATMF_PHYS_QRY_TSET (1 << 8)
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#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
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#define HPSATMF_MASK_SUPPORTED (1 << 16)
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#define HPSATMF_LOG_LUN_RESET (1 << 17)
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#define HPSATMF_LOG_NEX_RESET (1 << 18)
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#define HPSATMF_LOG_TASK_ABORT (1 << 19)
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#define HPSATMF_LOG_TSET_ABORT (1 << 20)
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#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
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#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
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#define HPSATMF_LOG_QRY_TASK (1 << 23)
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#define HPSATMF_LOG_QRY_TSET (1 << 24)
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#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
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u32 events;
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#define CTLR_STATE_CHANGE_EVENT (1 << 0)
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#define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
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#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
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#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
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#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
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#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
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#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
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#define RESCAN_REQUIRED_EVENT_BITS \
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(CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
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CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
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CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
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CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
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CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
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spinlock_t offline_device_lock;
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struct list_head offline_device_list;
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int acciopath_status;
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int raid_offload_debug;
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struct workqueue_struct *resubmit_wq;
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};
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struct offline_device_entry {
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unsigned char scsi3addr[8];
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struct list_head offline_list;
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};
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#define HPSA_ABORT_MSG 0
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#define HPSA_DEVICE_RESET_MSG 1
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#define HPSA_RESET_TYPE_CONTROLLER 0x00
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#define HPSA_RESET_TYPE_BUS 0x01
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#define HPSA_RESET_TYPE_TARGET 0x03
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#define HPSA_RESET_TYPE_LUN 0x04
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#define HPSA_MSG_SEND_RETRY_LIMIT 10
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#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
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/* Maximum time in seconds driver will wait for command completions
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* when polling before giving up.
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*/
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#define HPSA_MAX_POLL_TIME_SECS (20)
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/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
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* how many times to retry TEST UNIT READY on a device
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* while waiting for it to become ready before giving up.
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* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
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* between sending TURs while waiting for a device
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* to become ready.
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*/
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#define HPSA_TUR_RETRY_LIMIT (20)
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#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
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/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
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* to become ready, in seconds, before giving up on it.
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* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
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* between polling the board to see if it is ready, in
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* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
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* HPSA_BOARD_READY_ITERATIONS are derived from those.
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*/
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#define HPSA_BOARD_READY_WAIT_SECS (120)
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#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
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#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
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#define HPSA_BOARD_READY_POLL_INTERVAL \
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((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
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#define HPSA_BOARD_READY_ITERATIONS \
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((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
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HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
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#define HPSA_BOARD_NOT_READY_ITERATIONS \
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((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
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HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
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#define HPSA_POST_RESET_PAUSE_MSECS (3000)
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#define HPSA_POST_RESET_NOOP_RETRIES (12)
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/* Defining the diffent access_menthods */
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/*
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* Memory mapped FIFO interface (SMART 53xx cards)
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*/
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#define SA5_DOORBELL 0x20
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#define SA5_REQUEST_PORT_OFFSET 0x40
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#define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
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#define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
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#define SA5_REPLY_INTR_MASK_OFFSET 0x34
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#define SA5_REPLY_PORT_OFFSET 0x44
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#define SA5_INTR_STATUS 0x30
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#define SA5_SCRATCHPAD_OFFSET 0xB0
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#define SA5_CTCFG_OFFSET 0xB4
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#define SA5_CTMEM_OFFSET 0xB8
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#define SA5_INTR_OFF 0x08
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#define SA5B_INTR_OFF 0x04
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#define SA5_INTR_PENDING 0x08
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#define SA5B_INTR_PENDING 0x04
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#define FIFO_EMPTY 0xffffffff
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#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
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#define HPSA_ERROR_BIT 0x02
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/* Performant mode flags */
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#define SA5_PERF_INTR_PENDING 0x04
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#define SA5_PERF_INTR_OFF 0x05
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#define SA5_OUTDB_STATUS_PERF_BIT 0x01
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#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
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#define SA5_OUTDB_CLEAR 0xA0
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#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
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#define SA5_OUTDB_STATUS 0x9C
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#define HPSA_INTR_ON 1
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#define HPSA_INTR_OFF 0
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/*
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* Inbound Post Queue offsets for IO Accelerator Mode 2
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*/
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#define IOACCEL2_INBOUND_POSTQ_32 0x48
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#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
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#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
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/*
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Send the command to the hardware
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*/
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static void SA5_submit_command(struct ctlr_info *h,
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struct CommandList *c)
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{
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writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
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(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
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}
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static void SA5_submit_command_no_read(struct ctlr_info *h,
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struct CommandList *c)
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{
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writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
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}
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static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
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struct CommandList *c)
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{
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if (c->cmd_type == CMD_IOACCEL2)
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writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
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else
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writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
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}
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/*
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* This card is the opposite of the other cards.
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* 0 turns interrupts on...
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* 0x08 turns them off...
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*/
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static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
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{
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if (val) { /* Turn interrupts on */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else { /* Turn them off */
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h->interrupts_enabled = 0;
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writel(SA5_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
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{
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if (val) { /* turn on interrupts */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else {
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h->interrupts_enabled = 0;
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writel(SA5_PERF_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
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{
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struct reply_queue_buffer *rq = &h->reply_queue[q];
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unsigned long register_value = FIFO_EMPTY;
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/* msi auto clears the interrupt pending bit. */
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if (unlikely(!(h->msi_vector || h->msix_vector))) {
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/* flush the controller write of the reply queue by reading
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* outbound doorbell status register.
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*/
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(void) readl(h->vaddr + SA5_OUTDB_STATUS);
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writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
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/* Do a read in order to flush the write to the controller
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* (as per spec.)
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*/
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(void) readl(h->vaddr + SA5_OUTDB_STATUS);
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}
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if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
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register_value = rq->head[rq->current_entry];
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rq->current_entry++;
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atomic_dec(&h->commands_outstanding);
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} else {
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register_value = FIFO_EMPTY;
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}
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/* Check for wraparound */
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if (rq->current_entry == h->max_commands) {
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rq->current_entry = 0;
|
|
rq->wraparound ^= 1;
|
|
}
|
|
return register_value;
|
|
}
|
|
|
|
/*
|
|
* returns value read from hardware.
|
|
* returns FIFO_EMPTY if there is nothing to read
|
|
*/
|
|
static unsigned long SA5_completed(struct ctlr_info *h,
|
|
__attribute__((unused)) u8 q)
|
|
{
|
|
unsigned long register_value
|
|
= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
|
|
|
|
if (register_value != FIFO_EMPTY)
|
|
atomic_dec(&h->commands_outstanding);
|
|
|
|
#ifdef HPSA_DEBUG
|
|
if (register_value != FIFO_EMPTY)
|
|
dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
|
|
register_value);
|
|
else
|
|
dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
|
|
#endif
|
|
|
|
return register_value;
|
|
}
|
|
/*
|
|
* Returns true if an interrupt is pending..
|
|
*/
|
|
static bool SA5_intr_pending(struct ctlr_info *h)
|
|
{
|
|
unsigned long register_value =
|
|
readl(h->vaddr + SA5_INTR_STATUS);
|
|
return register_value & SA5_INTR_PENDING;
|
|
}
|
|
|
|
static bool SA5_performant_intr_pending(struct ctlr_info *h)
|
|
{
|
|
unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
|
|
|
|
if (!register_value)
|
|
return false;
|
|
|
|
/* Read outbound doorbell to flush */
|
|
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
|
|
return register_value & SA5_OUTDB_STATUS_PERF_BIT;
|
|
}
|
|
|
|
#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
|
|
|
|
static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
|
|
{
|
|
unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
|
|
|
|
return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
|
|
true : false;
|
|
}
|
|
|
|
#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
|
|
#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
|
|
#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
|
|
#define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
|
|
|
|
static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
|
|
{
|
|
u64 register_value;
|
|
struct reply_queue_buffer *rq = &h->reply_queue[q];
|
|
|
|
BUG_ON(q >= h->nreply_queues);
|
|
|
|
register_value = rq->head[rq->current_entry];
|
|
if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
|
|
rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
|
|
if (++rq->current_entry == rq->size)
|
|
rq->current_entry = 0;
|
|
/*
|
|
* @todo
|
|
*
|
|
* Don't really need to write the new index after each command,
|
|
* but with current driver design this is easiest.
|
|
*/
|
|
wmb();
|
|
writel((q << 24) | rq->current_entry, h->vaddr +
|
|
IOACCEL_MODE1_CONSUMER_INDEX);
|
|
atomic_dec(&h->commands_outstanding);
|
|
}
|
|
return (unsigned long) register_value;
|
|
}
|
|
|
|
static struct access_method SA5_access = {
|
|
SA5_submit_command,
|
|
SA5_intr_mask,
|
|
SA5_intr_pending,
|
|
SA5_completed,
|
|
};
|
|
|
|
static struct access_method SA5_ioaccel_mode1_access = {
|
|
SA5_submit_command,
|
|
SA5_performant_intr_mask,
|
|
SA5_ioaccel_mode1_intr_pending,
|
|
SA5_ioaccel_mode1_completed,
|
|
};
|
|
|
|
static struct access_method SA5_ioaccel_mode2_access = {
|
|
SA5_submit_command_ioaccel2,
|
|
SA5_performant_intr_mask,
|
|
SA5_performant_intr_pending,
|
|
SA5_performant_completed,
|
|
};
|
|
|
|
static struct access_method SA5_performant_access = {
|
|
SA5_submit_command,
|
|
SA5_performant_intr_mask,
|
|
SA5_performant_intr_pending,
|
|
SA5_performant_completed,
|
|
};
|
|
|
|
static struct access_method SA5_performant_access_no_read = {
|
|
SA5_submit_command_no_read,
|
|
SA5_performant_intr_mask,
|
|
SA5_performant_intr_pending,
|
|
SA5_performant_completed,
|
|
};
|
|
|
|
struct board_type {
|
|
u32 board_id;
|
|
char *product_name;
|
|
struct access_method *access;
|
|
};
|
|
|
|
#endif /* HPSA_H */
|
|
|