Wei Li aa638cfe3e arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list
HiSilicon Taishan v110 CPUs didn't implement CSV2 field of the
ID_AA64PFR0_EL1, but spectre-v2 is mitigated by hardware, so
whitelist the MIDR in the safe list.

Signed-off-by: Wei Li <liwei391@huawei.com>
[hanjun: re-write the commit log]
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-12-20 17:57:22 +00:00
..
2019-07-08 09:54:55 -07:00
2019-11-06 14:17:34 +00:00
2019-07-08 09:54:55 -07:00
2019-12-06 13:25:14 +00:00
2019-11-06 14:17:36 +00:00
2019-11-25 19:40:40 -08:00
2019-07-08 09:54:55 -07:00
2019-10-28 11:22:47 +00:00
2019-11-06 14:17:35 +00:00
2019-07-15 20:44:49 -07:00
2019-10-10 14:55:24 -07:00
2019-04-23 18:01:57 +01:00
2019-12-06 14:18:01 -08:00
2019-12-06 14:18:01 -08:00