c2df436bd2
* One new edac driver for Intel E3-12xx DRAM controllers. Out-of-subsystem changes are making the non-atomic iomem 64-bit accessors' naming explicit to show both exact order of the 32-bit accesses and the non-atomicity of the 64-bit access. Usage locations are more verbose now as to what access is exactly being done vs having a not-very telling "readq" there, for example. This is needed by E3-12xx hardware where certain mmapped registers cannot be accessed with requests crossing a dword boundary. From Jason Baron. * Extending AMD MCE signatures to a new model 60h in family 15h, from Aravind Gopalakrishnan. * An unsigned check cleanup, from Fabian Frederick. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJT3zk+AAoJEBLB8Bhh3lVKZxYP/A1y+lumv9HwR8lcP5nfyJ9N oruQDzJ7hrOSVHK2nRUO2rpJRPZ7FDFB6rM1aTvi+BwxOrNuaPeDJPTMUyQjJHKg bZ7cAbOnmkSTrg314+cZkODD2qHUlznRx6vpVZRSHxaWyTp4ILrst5b/0i2ktduF OyRswngAJixJzweqdwY/9hBvYAZVt96eME2Yt6HoP/vHAZQOCpDAGFqJ5KtCrqyk Pu/wKHbnQNLk6x8r6NI+gh1ZKnGtv5WGGwMArOZF7f/wJ3VVvRamLphhzVkQr6yC DMVyBVgVngPip0LkiPHMYcgWuUwYdnBM3Wu3Gd+jlNqaX2q3Ach7ljwOwcRCFQDz QDgf4/lhAQ822u7s+aYIpcd4x6K7KRSNJk1TOj1KlpMWI3IxIizC+jCNeWpkT21p zgkhom76Q4kw7HEAyCuDTDNOA8WNH0zw8C4+SFtz0VVoo4WNU8+dYckiE1ZYCInS UQ9dkOe+rSTHQw47uoB2/bmuDB/dSuleamVkkAoqMvXnMZg0Ag4C02iqGat/pqi7 m3eDTng4DAhayYxqlqU8/pZPRd+QliR5jqEuqPJEIAXMINl+9ZMEAVebtHOJrhW5 5sF73SZG9zZfnczG756ahNxIZ0VXmRQoa+AmReHOyLQhms2DYqteN0aEYDVzD1Zb IqXin85i8ZLehto/Umrq =KmeT -----END PGP SIGNATURE----- Merge tag 'edac_for_3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp Pull EDAC changes from Borislav Petkov: "EDAC queue for 3.17: - One new edac driver for Intel E3-12xx DRAM controllers. - Out-of-subsystem changes are making the non-atomic iomem 64-bit accessors' naming explicit to show both exact order of the 32-bit accesses and the non-atomicity of the 64-bit access. Usage locations are more verbose now as to what access is exactly being done vs having a not-very telling "readq" there, for example. This is needed by E3-12xx hardware where certain mmapped registers cannot be accessed with requests crossing a dword boundary. From Jason Baron. - Extending AMD MCE signatures to a new model 60h in family 15h, from Aravind Gopalakrishnan. - An unsigned check cleanup, from Fabian Frederick" * tag 'edac_for_3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: EDAC, MCE, AMD: Add MCE decoding for F15h M60h MAINTAINERS: add ie31200_edac entry ie31200_edac: Allocate mci and map mchbar first ie31200_edac: Introduce the driver x38_edac: make use of lo_hi_readq() readq/writeq: Add explicit lo_hi_[read|write]_q and hi_lo_[read|write]_q EDAC, edac_module.c: Remove unnecessary test on unsigned value