448e9cb363
Add a resource identifier for maximum number of FIDs so that it could be later used to query the information from firmware. In Spectrum-2 and Spectrum-3, the correction field of PTP packets which are sent as control packets is not updated at egress port. To overcome this limitation, some packets will be sent as data packets. The header should include FID, which is supposed to be 'Max FID + port - 1'. As preparation, add the required resource, to be able to query the value from firmware later. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
169 lines
5.1 KiB
C
169 lines
5.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
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/* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
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#ifndef _MLXSW_RESOURCES_H
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#define _MLXSW_RESOURCES_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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enum mlxsw_res_id {
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MLXSW_RES_ID_KVD_SIZE,
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MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
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MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
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MLXSW_RES_ID_PGT_SIZE,
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MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE,
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MLXSW_RES_ID_MAX_KVD_ACTION_SETS,
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MLXSW_RES_ID_MAX_TRAP_GROUPS,
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MLXSW_RES_ID_CQE_V0,
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MLXSW_RES_ID_CQE_V1,
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MLXSW_RES_ID_CQE_V2,
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MLXSW_RES_ID_COUNTER_POOL_SIZE,
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MLXSW_RES_ID_COUNTER_BANK_SIZE,
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MLXSW_RES_ID_MAX_SPAN,
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MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
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MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
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MLXSW_RES_ID_MAX_SYSTEM_PORT,
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MLXSW_RES_ID_FID,
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MLXSW_RES_ID_MAX_LAG,
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MLXSW_RES_ID_MAX_LAG_MEMBERS,
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MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER,
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MLXSW_RES_ID_CELL_SIZE,
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MLXSW_RES_ID_MAX_HEADROOM_SIZE,
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MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
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MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
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MLXSW_RES_ID_ACL_MAX_REGIONS,
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MLXSW_RES_ID_ACL_MAX_GROUPS,
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MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
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MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS,
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MLXSW_RES_ID_ACL_FLEX_KEYS,
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MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
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MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
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MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,
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MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,
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MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
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MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB,
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MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB,
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MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB,
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MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB,
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MLXSW_RES_ID_ACL_MAX_BF_LOG,
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MLXSW_RES_ID_MAX_GLOBAL_POLICERS,
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MLXSW_RES_ID_MAX_CPU_POLICERS,
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MLXSW_RES_ID_MAX_VRS,
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MLXSW_RES_ID_MAX_RIFS,
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MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES,
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MLXSW_RES_ID_MAX_RIF_MAC_PROFILES,
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MLXSW_RES_ID_MAX_LPM_TREES,
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MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4,
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MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6,
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/* Internal resources.
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* Determined by the SW, not queried from the HW.
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*/
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MLXSW_RES_ID_KVD_SINGLE_SIZE,
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MLXSW_RES_ID_KVD_DOUBLE_SIZE,
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MLXSW_RES_ID_KVD_LINEAR_SIZE,
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__MLXSW_RES_ID_MAX,
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};
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static u16 mlxsw_res_ids[] = {
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[MLXSW_RES_ID_KVD_SIZE] = 0x1001,
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[MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
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[MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
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[MLXSW_RES_ID_PGT_SIZE] = 0x1004,
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[MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005,
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[MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007,
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[MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
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[MLXSW_RES_ID_CQE_V0] = 0x2210,
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[MLXSW_RES_ID_CQE_V1] = 0x2211,
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[MLXSW_RES_ID_CQE_V2] = 0x2212,
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[MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
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[MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411,
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[MLXSW_RES_ID_MAX_SPAN] = 0x2420,
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[MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
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[MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
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[MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
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[MLXSW_RES_ID_FID] = 0x2512,
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[MLXSW_RES_ID_MAX_LAG] = 0x2520,
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[MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
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[MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805, /* Bytes */
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[MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */
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[MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811, /* Bytes */
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[MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
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[MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
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[MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
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[MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
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[MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
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[MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS] = 0x2908,
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[MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
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[MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
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[MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
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[MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,
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[MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,
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[MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,
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[MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950,
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[MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951,
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[MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952,
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[MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953,
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[MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960,
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[MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10,
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[MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
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[MLXSW_RES_ID_MAX_VRS] = 0x2C01,
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[MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
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[MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10,
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[MLXSW_RES_ID_MAX_RIF_MAC_PROFILES] = 0x2C14,
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[MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
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[MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02,
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[MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03,
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};
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struct mlxsw_res {
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bool valid[__MLXSW_RES_ID_MAX];
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u64 values[__MLXSW_RES_ID_MAX];
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};
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static inline bool mlxsw_res_valid(struct mlxsw_res *res,
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enum mlxsw_res_id res_id)
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{
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return res->valid[res_id];
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}
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#define MLXSW_RES_VALID(res, short_res_id) \
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mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
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static inline u64 mlxsw_res_get(struct mlxsw_res *res,
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enum mlxsw_res_id res_id)
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{
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if (WARN_ON(!res->valid[res_id]))
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return 0;
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return res->values[res_id];
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}
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#define MLXSW_RES_GET(res, short_res_id) \
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mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
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static inline void mlxsw_res_set(struct mlxsw_res *res,
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enum mlxsw_res_id res_id, u64 value)
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{
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res->valid[res_id] = true;
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res->values[res_id] = value;
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}
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#define MLXSW_RES_SET(res, short_res_id, value) \
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mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
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static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
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if (mlxsw_res_ids[i] == id) {
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mlxsw_res_set(res, i, value);
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return;
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}
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}
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}
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#endif
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