4b7a632ac4
Both RIF and ACL flow counters use a 24-bit SW-managed counter address to
communicate which counter they want to bind.
In a number of Spectrum FW releases, binding a RIF counter is broken and
slices the counter index to 16 bits. As a result, on Spectrum-2 and above,
no more than about 410 RIF counters can be effectively used. This
translates to 205 netdevices for which L3 HW stats can be enabled. (This
does not happen on Spectrum-1, because there are fewer counters available
overall and the counter index never exceeds 16 bits.)
Binding counters to ACLs does not have this issue. Therefore reorder the
counter allocation scheme so that RIF counters come first and therefore get
lower indices that are below the 16-bit barrier.
Fixes: 98e60dce4da1 ("Merge branch 'mlxsw-Introduce-initial-Spectrum-2-support'")
Reported-by: Maksym Yaremchuk <maksymy@nvidia.com>
Signed-off-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/20220613125017.2018162-1-idosch@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
26 lines
822 B
C
26 lines
822 B
C
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
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/* Copyright (c) 2017-2018 Mellanox Technologies. All rights reserved */
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#ifndef _MLXSW_SPECTRUM_CNT_H
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#define _MLXSW_SPECTRUM_CNT_H
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#include "core.h"
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#include "spectrum.h"
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enum mlxsw_sp_counter_sub_pool_id {
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MLXSW_SP_COUNTER_SUB_POOL_RIF,
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MLXSW_SP_COUNTER_SUB_POOL_FLOW,
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};
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int mlxsw_sp_counter_alloc(struct mlxsw_sp *mlxsw_sp,
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enum mlxsw_sp_counter_sub_pool_id sub_pool_id,
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unsigned int *p_counter_index);
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void mlxsw_sp_counter_free(struct mlxsw_sp *mlxsw_sp,
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enum mlxsw_sp_counter_sub_pool_id sub_pool_id,
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unsigned int counter_index);
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int mlxsw_sp_counter_pool_init(struct mlxsw_sp *mlxsw_sp);
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void mlxsw_sp_counter_pool_fini(struct mlxsw_sp *mlxsw_sp);
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int mlxsw_sp_counter_resources_register(struct mlxsw_core *mlxsw_core);
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#endif
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