Nanyong Sun c3b2d67046 riscv: mm: add param stride for __sbi_tlb_flush_range ... Add a parameter: stride for __sbi_tlb_flush_range(), represent the page stride between the address of start and end. Normally, the stride is PAGE_SIZE, and when flush huge page address, the stride can be the huge page size such as:PMD_SIZE, then it only need to flush one tlb entry if the address range within PMD_SIZE. Signed-off-by: Nanyong Sun <sunnanyong@huawei.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-05-22 10:19:47 -07:00
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boot	RISC-V Patches for the 5.13 Merge Window, Part 1	2021-05-06 09:24:18 -07:00
configs	RISC-V: Enable Microchip PolarFire ICICLE SoC	2021-04-26 08:31:32 -07:00
errata	riscv: sifive: Apply errata "cip-1200" patch	2021-04-26 08:24:58 -07:00
include	riscv: mm: make pmd_bad() check leaf condition	2021-05-22 10:19:38 -07:00
kernel	riscv: remove unused handle_exception symbol	2021-05-06 09:40:16 -07:00
lib	riscv: Add support for function error injection	2021-01-14 15:09:09 -08:00
mm	riscv: mm: add param stride for __sbi_tlb_flush_range	2021-05-22 10:19:47 -07:00
net	riscv: bpf: Avoid breaking W^X	2021-04-26 08:25:14 -07:00
Kbuild	riscv: Allow device trees to be built into the kernel	2020-05-18 11:38:05 -07:00
Kconfig	RISC-V Patches for the 5.13 Merge Window, Part 1	2021-05-06 09:24:18 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.erratas	riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y	2021-05-06 09:40:13 -07:00
Kconfig.socs	RISC-V Patches for the 5.13 Merge Window, Part 1	2021-05-06 09:24:18 -07:00
Makefile	RISC-V: enable XIP	2021-04-26 08:31:28 -07:00