Charlene Liu c46e5df4ac drm/amd/display: dce11.x /dce12 update formula input ...

[Description]
1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update)
2. using memory type to convert UMC's MCLK to Yclk.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2019-09-17 14:35:41 -05:00

..

hw

drm/amd/display: add dcn21 core DC changes

2019-08-29 15:52:33 -05:00

bw_fixed.h

drm/amd/display: explicit uint64_t casting

2018-11-05 14:20:50 -05:00

clock_source.h

drm/amd/display: Keep clocks high before seamless boot done

2019-03-19 15:04:03 -05:00

compressor.h

drm/amd/display: fbc state could not reach while enable fbc

2018-11-30 12:02:35 -05:00

core_status.h

drm/amd/display: add set and get clock for testing purposes

2019-07-18 14:27:25 -05:00

core_types.h

drm/amd/display: add dcn21 core DC changes

2019-08-29 15:52:33 -05:00

custom_float.h

drm/amd/display: Enable regamma 25 segments and use double buffer.

2017-09-26 17:14:18 -04:00

dc_link_ddc.h

drm/amd/display: Respect aux return values

2019-03-19 15:04:02 -05:00

dc_link_dp.h

drm/amd/display: check hpd before retry verify link cap

2019-08-15 10:57:24 -05:00

dce_calcs.h

drm/amdgpu/display: remove VEGAM config option

2018-05-18 16:08:18 -05:00

dcn_calcs.h

drm/amd/display: make clk mgr soc specific

2019-05-31 10:39:29 -05:00

hw_sequencer.h

drm/amd/display: add dcn21 core DC changes

2019-08-29 15:52:33 -05:00

link_hwss.h

drm/amd/display: Synchronous DisplayPort Link Training

2019-08-15 10:53:30 -05:00

reg_helper.h

drm/amd/display: Combine field toggle macro and sequence write macro.

2019-03-19 15:36:49 -05:00

resource.h

drm/amd/display: dce11.x /dce12 update formula input

2019-09-17 14:35:41 -05:00

vm_helper.h

drm/amd/display: move vmid determination logic to a module

2019-06-22 09:34:14 -05:00