d79fa0a6d8
Originally, we consider weight only based on how many chanctxs that mac80211 sets. However, we need to consider both active chanctxs and active interfaces to distinguish MCC (multiple channel concurrent) from impending MLO. Although the logic of handling is extended, for now, behavior might not be different under current condition. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240206030624.23382-5-pkshih@realtek.com
112 lines
3.5 KiB
C
112 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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* Copyright(c) 2020-2022 Realtek Corporation
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*/
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#ifndef __RTW89_CHAN_H__
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#define __RTW89_CHAN_H__
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#include "core.h"
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/* The dwell time in TU before doing rtw89_chanctx_work(). */
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#define RTW89_CHANCTX_TIME_MCC_PREPARE 100
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#define RTW89_CHANCTX_TIME_MCC 100
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/* various MCC setting time in TU */
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#define RTW89_MCC_LONG_TRIGGER_TIME 300
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#define RTW89_MCC_SHORT_TRIGGER_TIME 100
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#define RTW89_MCC_EARLY_TX_BCN_TIME 10
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#define RTW89_MCC_EARLY_RX_BCN_TIME 5
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#define RTW89_MCC_MIN_RX_BCN_TIME 10
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#define RTW89_MCC_DFLT_BCN_OFST_TIME 40
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#define RTW89_MCC_MIN_GO_DURATION \
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(RTW89_MCC_EARLY_TX_BCN_TIME + RTW89_MCC_MIN_RX_BCN_TIME)
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#define RTW89_MCC_MIN_STA_DURATION \
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(RTW89_MCC_EARLY_RX_BCN_TIME + RTW89_MCC_MIN_RX_BCN_TIME)
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#define RTW89_MCC_DFLT_GROUP 0
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#define RTW89_MCC_NEXT_GROUP(cur) (((cur) + 1) % 4)
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#define RTW89_MCC_DFLT_TX_NULL_EARLY 3
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#define RTW89_MCC_DFLT_COURTESY_SLOT 3
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#define NUM_OF_RTW89_MCC_ROLES 2
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enum rtw89_chanctx_pause_reasons {
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RTW89_CHANCTX_PAUSE_REASON_HW_SCAN,
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RTW89_CHANCTX_PAUSE_REASON_ROC,
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};
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struct rtw89_entity_weight {
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unsigned int active_chanctxs;
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unsigned int active_roles;
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};
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static inline bool rtw89_get_entity_state(struct rtw89_dev *rtwdev)
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{
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struct rtw89_hal *hal = &rtwdev->hal;
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return READ_ONCE(hal->entity_active);
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}
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static inline void rtw89_set_entity_state(struct rtw89_dev *rtwdev, bool active)
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{
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struct rtw89_hal *hal = &rtwdev->hal;
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WRITE_ONCE(hal->entity_active, active);
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}
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static inline
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enum rtw89_entity_mode rtw89_get_entity_mode(struct rtw89_dev *rtwdev)
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{
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struct rtw89_hal *hal = &rtwdev->hal;
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return READ_ONCE(hal->entity_mode);
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}
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static inline void rtw89_set_entity_mode(struct rtw89_dev *rtwdev,
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enum rtw89_entity_mode mode)
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{
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struct rtw89_hal *hal = &rtwdev->hal;
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WRITE_ONCE(hal->entity_mode, mode);
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}
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void rtw89_chan_create(struct rtw89_chan *chan, u8 center_chan, u8 primary_chan,
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enum rtw89_band band, enum rtw89_bandwidth bandwidth);
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bool rtw89_assign_entity_chan(struct rtw89_dev *rtwdev,
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enum rtw89_sub_entity_idx idx,
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const struct rtw89_chan *new);
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void rtw89_config_entity_chandef(struct rtw89_dev *rtwdev,
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enum rtw89_sub_entity_idx idx,
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const struct cfg80211_chan_def *chandef);
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void rtw89_config_roc_chandef(struct rtw89_dev *rtwdev,
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enum rtw89_sub_entity_idx idx,
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const struct cfg80211_chan_def *chandef);
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void rtw89_entity_init(struct rtw89_dev *rtwdev);
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enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev);
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void rtw89_chanctx_work(struct work_struct *work);
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void rtw89_queue_chanctx_work(struct rtw89_dev *rtwdev);
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void rtw89_queue_chanctx_change(struct rtw89_dev *rtwdev,
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enum rtw89_chanctx_changes change);
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void rtw89_chanctx_track(struct rtw89_dev *rtwdev);
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void rtw89_chanctx_pause(struct rtw89_dev *rtwdev,
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enum rtw89_chanctx_pause_reasons rsn);
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void rtw89_chanctx_proceed(struct rtw89_dev *rtwdev);
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int rtw89_chanctx_ops_add(struct rtw89_dev *rtwdev,
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struct ieee80211_chanctx_conf *ctx);
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void rtw89_chanctx_ops_remove(struct rtw89_dev *rtwdev,
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struct ieee80211_chanctx_conf *ctx);
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void rtw89_chanctx_ops_change(struct rtw89_dev *rtwdev,
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struct ieee80211_chanctx_conf *ctx,
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u32 changed);
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int rtw89_chanctx_ops_assign_vif(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif,
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struct ieee80211_chanctx_conf *ctx);
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void rtw89_chanctx_ops_unassign_vif(struct rtw89_dev *rtwdev,
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struct rtw89_vif *rtwvif,
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struct ieee80211_chanctx_conf *ctx);
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#endif
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