Charlene Liu c7299705e6 drm/amd/display: only polling VSync Phase within VSync peroroid ...

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2017-09-26 18:17:17 -04:00

..

hw

drm/amd/display: only polling VSync Phase within VSync peroroid

2017-09-26 18:17:17 -04:00

bw_fixed.h

…

clock_source.h

drm/amd/display: add display write back(DWB)

2017-09-26 18:16:36 -04:00

compressor.h

drm/amd/display: Initial prototype of FBC implementation

2017-09-26 18:15:56 -04:00

core_status.h

drm/amd/display: Continue with stream enable if DP link training fails.

2017-09-26 18:06:58 -04:00

core_types.h

drm/amd/display: Move dis_clk into dc_state.

2017-09-26 18:17:16 -04:00

custom_float.h

drm/amd/display: Enable regamma 25 segments and use double buffer.

2017-09-26 17:14:18 -04:00

dc_link_ddc.h

drm/amd/display: Roll core_link into dc_link

2017-09-26 18:15:36 -04:00

dc_link_dp.h

drm/amd/display: Rename dc_stream to dc_stream_state

2017-09-26 18:16:04 -04:00

dce_calcs.h

drm/amd/display: Rename dc validate_context and current_context

2017-09-26 18:17:14 -04:00

dcn_calcs.h

drm/amd/display: Rename dc validate_context and current_context

2017-09-26 18:17:14 -04:00

hw_sequencer.h

drm/amd/display: Rename dc validate_context and current_context

2017-09-26 18:17:14 -04:00

link_hwss.h

drm/amd/display: Roll core_link into dc_link

2017-09-26 18:15:36 -04:00

reg_helper.h

drm/amd/display: add line number to reg_wait timeout print

2017-09-26 18:15:11 -04:00

resource.h

drm/amd/display: Rename dc validate_context and current_context

2017-09-26 18:17:14 -04:00