215ed2009c
Add the soc ids for additional xway socs. The patch also merges the amazon_se code with the other socs. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
116 lines
2.4 KiB
C
116 lines
2.4 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/export.h>
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#include <linux/clk.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <lantiq_soc.h>
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#include "../prom.h"
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#define SOC_DANUBE "Danube"
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#define SOC_TWINPASS "Twinpass"
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#define SOC_AMAZON_SE "Amazon_SE"
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#define SOC_AR9 "AR9"
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#define SOC_GR9 "GR9"
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#define SOC_VR9 "VR9"
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#define COMP_DANUBE "lantiq,danube"
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#define COMP_TWINPASS "lantiq,twinpass"
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#define COMP_AMAZON_SE "lantiq,ase"
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#define COMP_AR9 "lantiq,ar9"
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#define COMP_GR9 "lantiq,gr9"
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#define COMP_VR9 "lantiq,vr9"
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#define PART_SHIFT 12
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#define PART_MASK 0x0FFFFFFF
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#define REV_SHIFT 28
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#define REV_MASK 0xF0000000
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void __init ltq_soc_detect(struct ltq_soc_info *i)
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{
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i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
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i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
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sprintf(i->rev_type, "1.%d", i->rev);
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switch (i->partnum) {
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case SOC_ID_DANUBE1:
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case SOC_ID_DANUBE2:
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i->name = SOC_DANUBE;
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i->type = SOC_TYPE_DANUBE;
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i->compatible = COMP_DANUBE;
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break;
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case SOC_ID_TWINPASS:
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i->name = SOC_TWINPASS;
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i->type = SOC_TYPE_DANUBE;
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i->compatible = COMP_TWINPASS;
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break;
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case SOC_ID_ARX188:
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case SOC_ID_ARX168_1:
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case SOC_ID_ARX168_2:
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case SOC_ID_ARX182:
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i->name = SOC_AR9;
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i->type = SOC_TYPE_AR9;
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i->compatible = COMP_AR9;
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break;
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case SOC_ID_GRX188:
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case SOC_ID_GRX168:
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i->name = SOC_GR9;
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i->type = SOC_TYPE_AR9;
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i->compatible = COMP_GR9;
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break;
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case SOC_ID_AMAZON_SE_1:
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case SOC_ID_AMAZON_SE_2:
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#ifdef CONFIG_PCI
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panic("ase is only supported for non pci kernels");
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#endif
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i->name = SOC_AMAZON_SE;
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i->type = SOC_TYPE_AMAZON_SE;
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i->compatible = COMP_AMAZON_SE;
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break;
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case SOC_ID_VRX282:
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case SOC_ID_VRX268:
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case SOC_ID_VRX288:
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i->name = SOC_VR9;
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i->type = SOC_TYPE_VR9;
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i->compatible = COMP_VR9;
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break;
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case SOC_ID_GRX268:
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case SOC_ID_GRX288:
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i->name = SOC_GR9;
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i->type = SOC_TYPE_VR9;
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i->compatible = COMP_GR9;
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break;
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case SOC_ID_VRX268_2:
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case SOC_ID_VRX288_2:
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i->name = SOC_VR9;
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i->type = SOC_TYPE_VR9_2;
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i->compatible = COMP_VR9;
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break;
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case SOC_ID_GRX282_2:
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case SOC_ID_GRX288_2:
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i->name = SOC_GR9;
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i->type = SOC_TYPE_VR9_2;
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i->compatible = COMP_GR9;
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break;
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default:
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unreachable();
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break;
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}
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}
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