Vincent Chen c82dd6d078 riscv: Avoid interrupts being erroneously enabled in handle_exception() ... When the handle_exception function addresses an exception, the interrupts will be unconditionally enabled after finishing the context save. However, It may erroneously enable the interrupts if the interrupts are disabled before entering the handle_exception. For example, one of the WARN_ON() condition is satisfied in the scheduling where the interrupt is disabled and rq.lock is locked. The WARN_ON will trigger a break exception and the handle_exception function will enable the interrupts before entering do_trap_break function. During the procedure, if a timer interrupt is pending, it will be taken when interrupts are enabled. In this case, it may cause a deadlock problem if the rq.lock is locked again in the timer ISR. Hence, the handle_exception() can only enable interrupts when the state of sstatus.SPIE is 1. This patch is tested on HiFive Unleashed board. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> [paul.walmsley@sifive.com: updated to apply] Fixes: bcae803a21 ("RISC-V: Enable IRQ during exception handling") Cc: David Abdurachmanov <david.abdurachmanov@sifive.com> Cc: stable@vger.kernel.org Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-09-20 08:42:34 -07:00
..
boot	riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes	2019-09-20 08:37:24 -07:00
configs	RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig	2019-09-19 05:44:35 -07:00
include	RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=y	2019-09-19 05:44:34 -07:00
kernel	riscv: Avoid interrupts being erroneously enabled in handle_exception()	2019-09-20 08:42:34 -07:00
lib	riscv: Using CSR numbers to access CSRs	2019-08-30 11:04:19 -07:00
mm	riscv: move the TLB flush logic out of line	2019-09-05 01:54:51 -07:00
net	bpf, riscv: Enable zext optimization for more RV64G ALU ops	2019-07-05 23:55:41 +02:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: select SiFive platform drivers with SOC_SIFIVE	2019-07-01 13:20:01 -07:00
Makefile	riscv: Add perf callchain support	2019-09-04 12:43:00 -07:00