cddacdce8f
Add binding and an extra property for Hi3798MV200 DWMMC specific extension. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Link: https://lore.kernel.org/r/20240229-b4-mmc-hi3798mv200-v7-4-10c03f316285@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
98 lines
2.5 KiB
YAML
98 lines
2.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Hisilicon HiSTB SoCs specific extensions to the Synopsys DWMMC controller
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maintainers:
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- Yang Xiwen <forbidden405@outlook.com>
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properties:
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compatible:
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enum:
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- hisilicon,hi3798cv200-dw-mshc
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- hisilicon,hi3798mv200-dw-mshc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: bus interface unit clock
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- description: card interface unit clock
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- description: card input sample phase clock
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- description: controller output drive phase clock
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clock-names:
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items:
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- const: ciu
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- const: biu
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- const: ciu-sample
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- const: ciu-drive
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hisilicon,sap-dll-reg:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path.
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It is integrated into CRG core on the SoC and has to be controlled during tuning.
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items:
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- description: A phandle pointed to the CRG syscon node
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- description: Sample DLL register offset in CRG address space
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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allOf:
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- $ref: synopsys-dw-mshc-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: hisilicon,hi3798mv200-dw-mshc
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then:
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required:
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- hisilicon,sap-dll-reg
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else:
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properties:
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hisilicon,sap-dll-reg: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/histb-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mmc@9830000 {
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compatible = "hisilicon,hi3798cv200-dw-mshc";
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reg = <0x9830000 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_MMC_CIU_CLK>,
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<&crg HISTB_MMC_BIU_CLK>,
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<&crg HISTB_MMC_SAMPLE_CLK>,
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<&crg HISTB_MMC_DRV_CLK>;
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clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
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resets = <&crg 0xa0 4>;
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reset-names = "reset";
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
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&emmc_pins_3 &emmc_pins_4>;
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fifo-depth = <256>;
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clock-frequency = <200000000>;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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non-removable;
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bus-width = <8>;
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};
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