b119194090
make CHECK_DTBS=y st/stm32f469-disco.dtb brings up a warning about a missing argument: stm32f469-disco.dtb: pinctrl@40020000: st,syscfg:0: [21, 8] is too short The description of the third entry indicates that this entry is optional. The code in stm32_pctrl_dt_setup_irq parses st,syscfg and treats the third entry as optional. It defaults to 0xf if not present in the devicetree. Update the schema to require at least two entries, use the same syntax as the description of renesas,ipmmu-main in Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231006082247.3830719-1-martin@kaiser.cx Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
290 lines
8.3 KiB
YAML
290 lines
8.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) STMicroelectronics 2019.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32 GPIO and Pin Mux/Config controller
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maintainers:
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- Alexandre TORGUE <alexandre.torgue@foss.st.com>
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description: |
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STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
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controller. It controls the input/output settings on the available pins and
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also provides ability to multiplex and configure the output of various
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on-chip controllers onto these pads.
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properties:
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compatible:
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enum:
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- st,stm32f429-pinctrl
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- st,stm32f469-pinctrl
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- st,stm32f746-pinctrl
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- st,stm32f769-pinctrl
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- st,stm32h743-pinctrl
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- st,stm32mp135-pinctrl
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- st,stm32mp157-pinctrl
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- st,stm32mp157-z-pinctrl
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- st,stm32mp257-pinctrl
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- st,stm32mp257-z-pinctrl
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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ranges: true
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pins-are-numbered:
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$ref: /schemas/types.yaml#/definitions/flag
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deprecated: true
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hwlocks: true
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interrupts:
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maxItems: 1
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st,syscfg:
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description: Phandle+args to the syscon node which includes IRQ mux selection.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- minItems: 2
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items:
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- description: syscon node which includes IRQ mux selection
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- description: The offset of the IRQ mux selection register
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- description: The field mask of IRQ mux, needed if different of 0xf
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st,package:
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description:
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Indicates the SOC package used.
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More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
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patternProperties:
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'^gpio@[0-9a-f]*$':
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type: object
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additionalProperties: false
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properties:
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gpio-controller: true
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'#gpio-cells':
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const: 2
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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gpio-line-names: true
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gpio-ranges:
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minItems: 1
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maxItems: 16
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ngpios:
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description:
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Number of available gpios in a bank.
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minimum: 1
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maximum: 16
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st,bank-name:
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description:
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Should be a name string for this bank as specified in the datasheet.
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$ref: /schemas/types.yaml#/definitions/string
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enum:
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- GPIOA
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- GPIOB
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- GPIOC
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- GPIOD
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- GPIOE
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- GPIOF
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- GPIOG
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- GPIOH
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- GPIOI
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- GPIOJ
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- GPIOK
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- GPIOZ
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st,bank-ioport:
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description:
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Should correspond to the EXTI IOport selection (EXTI line used
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to select GPIOs as interrupts).
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 11
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patternProperties:
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"^(.+-hog(-[0-9]+)?)$":
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type: object
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required:
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- gpio-hog
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required:
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- gpio-controller
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- '#gpio-cells'
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- reg
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- clocks
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- st,bank-name
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'-[0-9]*$':
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type: object
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additionalProperties: false
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patternProperties:
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'^pins':
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type: object
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additionalProperties: false
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description: |
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A pinctrl node should contain at least one subnode representing the
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pinctrl group available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive, output high/low and output speed.
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properties:
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pinmux:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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Integer array, represents gpio pin number and mux setting.
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Supported pin number and mux varies for different SoCs, and are
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defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
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These defines are calculated as: ((port * 16 + line) << 8) | function
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With:
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- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
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- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
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- function: The function number, can be:
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* 0 : GPIO
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* 1 : Alternate Function 0
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* 2 : Alternate Function 1
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* 3 : Alternate Function 2
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* ...
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* 16 : Alternate Function 15
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* 17 : Analog
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To simplify the usage, macro is available to generate "pinmux" field.
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This macro is available here:
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- include/dt-bindings/pinctrl/stm32-pinfunc.h
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Some examples of using macro:
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/* GPIO A9 set as alernate function 2 */
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... {
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pinmux = <STM32_PINMUX('A', 9, AF2)>;
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};
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/* GPIO A9 set as GPIO */
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... {
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pinmux = <STM32_PINMUX('A', 9, GPIO)>;
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};
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/* GPIO A9 set as analog */
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... {
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pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
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};
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bias-disable:
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type: boolean
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bias-pull-down:
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type: boolean
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bias-pull-up:
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type: boolean
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drive-push-pull:
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type: boolean
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drive-open-drain:
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type: boolean
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output-low:
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type: boolean
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output-high:
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type: boolean
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slew-rate:
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description: |
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0: Low speed
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1: Medium speed
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2: Fast speed
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3: High speed
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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required:
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- pinmux
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allOf:
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- $ref: pinctrl.yaml#
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required:
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- compatible
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- '#address-cells'
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- '#size-cells'
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/mfd/stm32f4-rcc.h>
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//Example 1
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pinctrl@40020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32f429-pinctrl";
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ranges = <0 0x40020000 0x3000>;
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gpioa: gpio@0 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x0 0x400>;
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resets = <&reset_ahb1 0>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
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st,bank-name = "GPIOA";
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};
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};
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//Example 2 (using gpio-ranges)
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pinctrl@50020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32f429-pinctrl";
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ranges = <0 0x50020000 0x3000>;
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gpiob: gpio@1000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1000 0x400>;
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resets = <&reset_ahb1 0>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
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st,bank-name = "GPIOB";
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gpio-ranges = <&pinctrl 0 0 16>;
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};
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gpioc: gpio@2000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x2000 0x400>;
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resets = <&reset_ahb1 0>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
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st,bank-name = "GPIOC";
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ngpios = <5>;
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gpio-ranges = <&pinctrl 0 16 3>,
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<&pinctrl 14 30 2>;
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};
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};
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//Example 3 pin groups
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pinctrl {
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usart1_pins_a: usart1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 9, AF7)>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 10, AF7)>;
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bias-disable;
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};
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};
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};
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usart1 {
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pinctrl-0 = <&usart1_pins_a>;
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pinctrl-names = "default";
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};
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...
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