1f2367a39f
D71 consists of a number of Register Blocks, every Block controls a specific HW function, every block has a common block_header to represent its type and pipeline information. GCU (Global Control Unit) is the first Block which describe the global information of D71 HW, Like number of block contained and the number of pipeline supported. So the d71_enum_resources parsed GCU and create pipeline according the GCU configuration, and then iterate and detect the blocks that indicated by the GCU and block_header. And this change also added two struct d71_dev/d71_pipeline to extend komeda_dev/komeda_pipeline to add some d71 only members. v2: - Return the specific errno not -1. - Use DRM_DEBUG as default debug msg printer. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
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* Author: James.Qian.Wang <james.qian.wang@arm.com>
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*
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*/
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#ifndef _D71_DEV_H_
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#define _D71_DEV_H_
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#include "komeda_dev.h"
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#include "komeda_pipeline.h"
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#include "d71_regs.h"
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struct d71_pipeline {
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struct komeda_pipeline base;
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/* d71 private pipeline blocks */
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u32 __iomem *lpu_addr;
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u32 __iomem *cu_addr;
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u32 __iomem *dou_addr;
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u32 __iomem *dou_ft_coeff_addr; /* forward transform coeffs table */
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};
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struct d71_dev {
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struct komeda_dev *mdev;
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int num_blocks;
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int num_pipelines;
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int num_rich_layers;
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u32 max_line_size;
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u32 max_vsize;
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u32 supports_dual_link : 1;
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u32 integrates_tbu : 1;
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/* global register blocks */
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u32 __iomem *gcu_addr;
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/* scaling coeffs table */
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u32 __iomem *glb_scl_coeff_addr[D71_MAX_GLB_SCL_COEFF];
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u32 __iomem *periph_addr;
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struct d71_pipeline *pipes[D71_MAX_PIPELINE];
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};
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#define to_d71_pipeline(x) container_of(x, struct d71_pipeline, base)
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int d71_probe_block(struct d71_dev *d71,
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struct block_header *blk, u32 __iomem *reg);
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void d71_read_block_header(u32 __iomem *reg, struct block_header *blk);
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#endif /* !_D71_DEV_H_ */
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